W83787IF Datasheet, PDF (61/123 Pages) Winbond – WINBOND I/O WITH SERIAL-INFRARED SUPPORT

W83787IF
7.2.1 Configuration Register 0 (CR0), EFER = 89H, EFIR = 0H
When EFER is loaded with 89H and EFIR with 0H, the CR0 register can be accessed through EFDR.
The bit definitions for CR0 are as follows:
7 6 54 3 2 1 0
OCSS0
OCSS1
PRTMODS0
PRTMODS1
FADSEL
FDCEN
HADSEL
IDEEN
Notes:
IDEEN (Bit 7):
This bit enables/disables the IDE port. At power-on reset, this bit will latch the value set on the
CS0 / IDEEN pin. If there is no setting, a default enable will be latched by this bit because of the pull-
down resistor on the CS0 /IDEEN pin.
0
Enables IDE port.
1
Disables IDE port.
HADSEL (Bit 6):
This bit selects the HDC port address. At power-on reset, this bit will latch the value set on the
CS1/HADSEL pin. If there is no setting, a default 1F0H-1F7H, 3F6H, 3F7H will be latched by this bit
because of the pull-up resistor on the CS1/HADSEL pin.
0
Selects address range 170H-177H, 376H, 377H for IDE.
1
Selects address range 1F0H-1F7H, 3F6H, 3F7H for IDE.
FDCEN (Bit 5):
This bit enables/disables the FDC port. At power-on reset, this bit will latch the value set on the
FDCEN pin. If there is no setting, a default enable will be latched by this bit because of the pull-down
resistor on the FDCEN pin.
0
Enables FDC port.
1
Disables FDC port (when FDC port is disabled, no clock will be input to this port in
order to save power)
FADSEL (Bit 4):
This bit is used to select the FDC port address. At power-on reset, this bit will latch the value set on
the DBENH/FADSEL pin. If there is no setting, a default 3F0H-3F7H will be latched by this bit
because of the pull-up resistor on the DBENH/FADSEL pin.
0
Selects address range 370H-377H.
1
Selects address range 3F0H-3F7H.
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Publication ReleaseDate:Sep 1995
Revision A1