W25M02GVZEIG-TR Datasheet, PDF (7/68 Pages) Winbond – 3V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS

W25M02GV
1. GENERAL DESCRIPTIONS
The W25M02GV (2 x 1G-bit) Serial MCP (Multi Chip Package) Flash memory is based on the W25N
Serial SLC NAND SpiFlash^® series by stacking two individual W25N01GV die into a standard 8-pin
package. It offers the highest memory density for the low pin-count package, as well as Concurrent
Operations in Serial Flash memory for the first time. The W25M SpiStack^® series is ideal for small form
factor system designs, and applications that demand high Program/Erase data throughput. All W25N
SpiFlash family devices are offered in space-saving packages which were impossible to use in the past for
the typical NAND flash memory.
The SpiStack^® product series introduces a new “Software Die Select (C2h)” instruction, and a factory
assigned “Die ID#” for each stacked die. Each W25N01GV die can be accessed independently even
though the interface is shared. The SpiStack^® feature only allows a single die to be Active and have
control of the SPI interface at any given time to avoid bus contention.
The W25M02GV supports the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI: Serial Clock,
Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up
to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and
416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions.
The W25M02GV provides a new Continuous Read Mode that allows for efficient access to the entire
memory array with a single Read command. This feature is ideal for code shadowing applications.
Additionally, the device supports JEDEC standard manufacturer and device ID, one 2,048-Byte Unique ID
page, one 2,048-Byte parameter page and ten 2,048-Byte OTP pages. To provide better NAND flash
memory manageability, user configurable internal ECC, bad block management are also available in
W25M02GV.
2. FEATURES
• New Family of SpiFlash Memories
– W25M02GV: 2x1G-bit / 2x128M-byte
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
– Compatible SPI serial flash commands
• Highest Performance Serial NAND Flash
– 104MHz Standard/Dual/Quad SPI clocks
– 208/416MHz equivalent Dual/Quad SPI
– 50MB/S continuous data transfer rate
– Fast Program/Erase performance
– More than 100,000 erase/program cycles
– More than 10-year data retention
• Efficient “Continuous Read Mode”⁽¹⁾
– Alternative method to the Buffer Read Mode
– No need to issue “Page Data Read” between
Read commands
– Allows direct read access to the entire array
• Flexible “Concurrent Operations”
– Independent single die access
– Allows “Read while Program/Erase”
– Allows “Multi Die Program/Erase”
– Improves Program/Erase throughput
• Low Power, Wide Temperature Range
– Single 2.7 to 3.6V supply
– 25mA active, 20µA standby current
– -40°C to +85°C operating range
• Flexible Architecture with 128KB blocks
– Uniform 128K-Byte Block Erase
– Flexible page data load methods
• Advanced Features
– On chip 1-Bit ECC for memory array
– ECC status bits indicate ECC results
– bad block management and LUT⁽²⁾ access
– Software and Hardware Write-Protect
– Power Supply Lock-Down and OTP protection
– 2KB Unique ID and 2KB parameter pages
– Ten 2KB OTP pages⁽³⁾
• Space Efficient Packaging
– 8-pad WSON 8x6-mm
– 24-ball TFBGA 8x6-mm
– Contact Winbond for other package options
Notes:
1. Only the Read command structures are different between
the “Continuous Read Mode” and the “Buffer Read Mode”,
all other commands are identical.
2. LUT stands for Look-Up Table.
3. OTP pages can only be programmed.
Publication Release Date: July 1, 2015
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Preliminary - Revision B