W25M02GVZEIG-TR Datasheet, PDF (35/68 Pages) Winbond – 3V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS

W25M02GV
8.2.10 Last ECC Failure Page Address (A9h)
To better manage the data integrity, W25M02GV implements internal ECC correction for the entire
memory array. When the ECC-E bit in the Status/Configuration Register is set to 1 (also power up
default), the internal ECC algorithm is enabled for all Program and Read operations. During a “Program
Execute” command for a specific page, the ECC algorithm will calculate the ECC information based on the
data inside the 2K-Byte data buffer and write the ECC data into the extra 64-Byte ECC area in the same
physical memory page.
During the Read operations, ECC information will be used to verify the data read out from the physical
memory array and possible corrections can be made to limited amount of data bits that contain errors. The
ECC Status Bits (ECC-1 & ECC-0) will also be set indicating the result of ECC calculation.
For the “Continuous Read Mode (BUF=0)” operation, multiple pages of main array data can be read out
continuously by issuing a single read command. Upon finishing the read operation, the ECC status bits
should be check to verify if there’s any ECC correction or un-correctable errors existed in the read out
data. If ECC-1 & ECC-0 equal to (1, 0) or (1, 1), the previous read out data contain one or more pages
that contain ECC un-correctable errors. The failure page address (or the last page address if it’s multiple
pages) can be obtained by issuing the “Last ECC failure Page Address” command as illustrated in Figure
13. The 16-bit Page Address that contains un-correctable ECC errors will be presented on the DO pin
following the instruction code “A9h” and 8-bit dummy clocks on the DI pin.
Figure 13. Last ECC Failure Page Address Instruction
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Publication Release Date: July 1, 2015
Preliminary - Revision B