W25M02GVZEIG-TR Datasheet, PDF (5/68 Pages) Winbond – 3V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS

W25M02GV
Table of Figures
Figure 1a. W25M02GV Pad Assignments, 8-pad WSON 8x6-mm (Package Code ZE).............................. 7
Figure 1b. W25M02GV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB & TC)................... 8
Figure 2a. W25M02GV Device Configuration ............................................................................................... 9
Figure 2b. Single Die W25N01GV Flash Memory Architecture and Addressing ........................................ 11
Figure 2c. W25M02GV Flash Memory Operation Diagram ........................................................................ 12
Figure 3a. Protection Register / Status Register-1 (Address Axh).............................................................. 15
Figure 3b. Configuration Register / Status Register-2 (Address Bxh)......................................................... 17
Figure 3c. Status Register-3 (Address Cxh) ............................................................................................... 19
Figure 4. Software Die Select Instruction .................................................................................................... 26
Figure 5. Device Reset Instruction .............................................................................................................. 27
Figure 6. Read JEDEC ID Instruction.......................................................................................................... 28
Figure 7. Read Status Register Instruction ................................................................................................. 29
Figure 8. Write Status Register-1/2/3 Instruction ........................................................................................ 30
Figure 9. Write Enable Instruction............................................................................................................... 31
Figure 10. Write Disable Instruction ............................................................................................................ 31
Figure 11. Bad Block Management Instruction ........................................................................................... 32
Figure 12. Read BBM Look Up Table Instruction........................................................................................ 33
Figure 13. Last ECC Failure Page Address Instruction .............................................................................. 34
Figure 14. 128KB Block Erase Instruction .................................................................................................. 35
Figure 15. Load / Random Load Program Data Instruction ........................................................................ 36
Figure 16. Quad Load / Quad Random Load Program Data Instruction..................................................... 37
Figure 17. Program Execute Instruction...................................................................................................... 38
Figure 18. Page Data Read Instruction ....................................................................................................... 39
Figure 19a. Read Data Instruction (Buffer Read Mode, BUF=1) ................................................................ 40
Figure 19b. Read Data Instruction (Continuous Read Mode, BUF=0) ........................................................ 40
Figure 20a. Fast Read Instruction (Buffer Read Mode, BUF=1) ................................................................. 41
Figure 20b. Fast Read Instruction (Continuous Read Mode, BUF=0) ........................................................ 41
Figure 21a. Fast Read with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ................................ 42
Figure 21b. Fast Read with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ....................... 42
Figure 22a. Fast Read Dual Output Instruction (Buffer Read Mode, BUF=1)............................................. 43
Figure 22b. Fast Read Dual Output Instruction (Continuous Read Mode, BUF=0) .................................... 43
Figure 23a. Fast Read Dual Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)............ 44
Figure 23b. Fast Read Dual Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ... 44
Figure 24a. Fast Read Quad Output Instruction (Buffer Read Mode, BUF=1) ........................................... 45
Figure 24b. Fast Read Quad Output Instruction (Continuous Read Mode, BUF=0)................................... 45
Publication Release Date: July 1, 2015
-4-
Preliminary - Revision B