W25M02GVZEIG-TR Datasheet, PDF (23/68 Pages) Winbond – 3V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS

W25M02GV
8. INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set for each stacked W25N01GV die consists of 28 basic
instructions that are fully controlled through the SPI bus (see Instruction Set Table1, 2). Instructions are
initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides
the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit
(MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 4
through 29. All read instructions can be completed after any clocked bit. However, all instructions that
Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been
clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent
writes. Additionally, while the device is performing Program or Erase operation, BBM management, Page
Data Read or OTP locking operations, BUSY bit will be high, and all instructions except for Read Status
Register or Read JEDEC ID will be ignored until the current operation cycle has completed.
8.1 Device ID and Instruction Set Tables
8.1.1 Manufacturer and Device Identification
MANUFACTURER ID
Winbond Serial Flash
(MF7 - MF0)
EFh
Device ID
Single Die W25N01GV
2x stacked
(ID15 - ID0)
AB21h
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Publication Release Date: July 1, 2015
Preliminary - Revision B