W25M02GVZEIG-TR Datasheet, PDF (18/68 Pages) Winbond – 3V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS

W25M02GV
7.2 Configuration Register / Status Register-2 (Volatile Writable)
Figure 3b. Configuration Register / Status Register-2 (Address Bxh)
7.2.1 One Time Program Lock Bit (OTP-L) – OTP lockable
In addition to the main memory array, W25M02GV also provides an OTP area for the system to store
critical data that cannot be changed once it’s locked. The OTP area consists of 10 pages of 2,112-Byte
each. The default data in the OTP area are FFh. Only Program command can be issued to the OTP area
to change the data from “1” to “0”, and data is not reversible (“0” to “1”) by the Erase command. Once the
correct data is programmed in and verified, the system developer can set OTP-L bit to 1, so that the entire
OTP area will be locked to prevent further alteration to the data.
7.2.2 Enter OTP Access Mode Bit (OTP-E) – Volatile Writable
The OTP-E bit must be set to 1 in order to use the standard Program/Read commands to access the OTP
area as well as to read the Unique ID / Parameter Page information. The default value after power up or a
RESET command is 0.
7.2.3 Status Register-1 Lock Bit (SR1-L) – OTP lockable
The SR1-L lock bit is used to OTP lock the values in the Protection Register (SR-1). Depending on the
settings in the SR-1, the device can be configured to have a portion of or up to the entire array to be write-
protected, and the setting can be OTP locked by setting SR1-L bit to 1. SR1-L bit can only be set to 1
permanently when SRP1 & SRP0 are set to (1,1), and OTP Access Mode must be entered (OTP-E=1) to
execute the programming. Please refer to 8.2.26 for detailed information.
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