W25M02GVZEIG-TR Datasheet, PDF (43/68 Pages) Winbond – 3V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS

W25M02GV
8.2.18 Fast Read with 4-Byte Address (0Ch)
The Fast Read instruction allows one or more data bytes to be sequentially read from the Data Buffer after
executing the Read Page Data instruction. The Fast Read instruction is initiated by driving the /CS pin low
and then shifting the instruction code “0Ch” followed by the 16-bit Column Address and 24-bit dummy
clocks (when BUF=1) or a 40-bit dummy clocks (when BUF=0) into the DI pin. After the address is
received, the data byte of the addressed Data Buffer location will be shifted out on the DO pin at the falling
edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next
higher address after each byte of data is shifted out allowing for a continuous stream of data. The
instruction is completed by driving /CS high.
The Fast Read instruction sequence is shown in Figure 21a & 21b. When BUF=1, the device is in the
Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by the 16-
bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output, the
output pin will become Hi-Z state. When BUF=0, the device is in the Continuous Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be
following and continues through the entire memory array. This allows using a single Read instruction to
read out the entire memory array and is also compatible to Winbond’s SpiFlash NOR flash memory
command sequence.
/CS
CLK
Mode 3
Mode 0
DI
(IO0)
DO
(IO1)
0
789
21 22 23
47 48
54 55 56
62 63
Instruction
0Ch
Column Address[15:0]
15 14 13
210
High Impedance
24 Dummy
Clocks
Data Out 1
Data Out 2
76
1076
* _{* = MSB}
*
107
*
Figure 21a. Fast Read with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
/CS
CLK
Mode 3
Mode 0
DI
(IO0)
DO
(IO1)
0
789
21 22 23
Instruction
0Ch
39 38 37
40 Dummy Clocks
26 25 24
High Impedance
47 48
54 55 56
62 63
0
Data Out 1
Data Out 2
76
1076
* _{* = MSB}
*
107
*
Figure 21b. Fast Read with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
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Publication Release Date: July 1, 2015
Preliminary - Revision B