W25M02GVZEIG-TR Datasheet, PDF(16/68 Page) Winbond – 3V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS

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W25M02GVZEIG-TR Datasheet, PDF (16/68 Pages) Winbond – 3V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS

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W25M02GV

7. PROTECTION, CONFIGURATION AND STATUS REGISTERS

Three Status Registers are provided for each stacked W25N01GV die: Protection Register (SR-1),

Configuration Register (SR-2) & Status Register (SR-3). Each register is accessed by Read Status

The Read Status Register instruction (05h / 0Fh) can be used to provide status on the availability of the

flash memory array, whether the device is write enabled or disabled, the state of write protection, Read

modes, Protection Register/OTP area lock status, Erase/Program results, ECC usage/status. The Write

Status Register instruction can be used to configure the device write protection features, Software/Hardware

write protection, Read modes, enable/disable ECC, Protection Register/OTP area lock. Write access to the

Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP0, SRP1), the

Write Enable instruction, and when WP-E is set to 1, the /WP pin.

7.1 Protection Register / Status Register-1 (Volatile Writable, OTP lockable)

Figure 3a. Protection Register / Status Register-1 (Address Axh)

7.1.1 Block Protect Bits (BP3, BP2, BP1, BP0, TB) â Volatile Writable, OTP lockable

The Block Protect bits (BP3, BP2, BP1, BP0 & TB) are volatile read/write bits in the status register-1 (S6,

S5, S4, S3 & S2) that provide Write Protection control and status. Block Protect bits can be set using the

Write Status Register Instruction. All, none or a portion of the memory array can be protected from

Program and Erase instructions (see Status Register Memory Protection table). The default values for the

Block Protection bits are 1 after power up to protect the entire array. If the SR1-L bit in the Configuration

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