W25M02GVZEIG-TR Datasheet, PDF (57/68 Pages) Winbond – 3V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS

W25M02GV
9.3 Power-up Power-down Timing Requirements
PARAMETER
VCC (min) to /CS Low
Time Delay Before Write Instruction
Write Inhibit Threshold Voltage
SYMBOL
tVSL⁽¹⁾
tPUW⁽¹⁾
VWI⁽¹⁾
SPEC
MIN
500
5
1.0
MAX
2.0
Note:
1. These parameters are characterized only.
VCC
VCC(max)
VCC(min)
/CS must track VCC
Reset State
VWI
0Fh/05h/9Fh/FFh are
the only commands allowed.
tVSL
tPUW
Device is fully accessible
(Page 0 with ECC is ready in Buffer)
UNIT
µs
ms
V
VCC
Figure 30a. Power-up Timing and Voltage Levels
/CS must track VCC
during VCC Ramp Up/Down
Time
/CS
Figure 30b. Power-up, Power-Down Requirement
Time
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Publication Release Date: July 1, 2015
Preliminary - Revision B