W25M02GVZEIG-TR Datasheet, PDF (10/68 Pages) Winbond – 3V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS

4. PIN DESCRIPTIONS
4.1 Serial MCP (SpiStack^®) Device Configuration
W25M02GV
/CS
CLK
W25N01GV
W25N01GV
Die #1
Die #0
W25M02GV (SpiStack^®)
IO₀ (DIO)
IO₁ (DO)
IO₂ (/WP)
IO₃ (/HOLD)
Figure 2a. W25M02GV Device Configuration
All signal pins are shared by the stacked dies within the package. Each die is assigned a “Die ID#” in the
factory. Only a single die is active at any given time, and have the control of the SPI bus to communicate
with the external SPI controller. However, all the dies will accept two instructions regardless their Active or
Idle status: 1) “Software Die Select (C2h)” instruction; it is used to set any single die to be active according
to the 8-bit Die ID following the instruction. 2) “Device Reset (FFh)” instruction; it is used to reset all the
stacked dies to their power-up state. Die #0 will always be Active after power-up or Device Reset.
4.2 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure
30b). If needed, a pull-up resistor on the /CS pin can be used to accomplish this.
4.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25M02GV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising
edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read
data or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge of
CLK.
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