TA1317AN Datasheet, PDF (52/59 Pages) Toshiba Semiconductor – TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic

Note
No.
Parameter
41 Vertical ramp cut level
TA1317AN
SW5
ON
SW6
A
SW7
OFF
Test Condition
SW Mode
SW8 SW10 SW11 SW17 SW24
Test Method
(unless otherwise specified, V_CC = 9 V, Ta = 25 ± 3°C, data = preset values)
OFF B
ON
A
A (1) Input vertical trigger pulse to pin V_IN.
Pulse level (VT) = 3.0 V
(2) Set VD (sub-address: 00) to DC-Coupling mode (data: 80).
(3) Set V INTEGRAL CORRECTION (sub-address: 08) to center (data: 8F).
(4) Set V S CORRECTION (sub-address: 09) to center (data: A0).
(5) Measure amplitudes V_T and V_B as shown in the figure below.
Pin 6
(V NF) waveform
10 ms
10 ms
(6) Set V-RAMP to maximum and measure amplitudes V_TH and V_BH.
Sub-address 04 data: 87
Sub-address 05 data: 81
Pin 6
(V NF) waveform
10 ms
10 ms
(7) Calculate cut levels using the following formulas.
V_CHL =
V_CLL =
V_T − V_TL
V_T
V_B − V_BL
V_B
× 100, V_CHH =
× 100, V_CLH =
V_T − V_TH
V_T
V_B − V_BH
V_B
× 100
× 100
52
2002-09-06