TA1317AN Datasheet, PDF (48/59 Pages) Toshiba Semiconductor – TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic

Note
No.
Parameter
31 Vertical DF amplitude
adjustment (V DF amp)
TA1317AN
SW5
OFF
SW6
B
SW7
ON
Test Condition
SW Mode
SW8 SW10 SW11 SW17 SW24
Test Method
(unless otherwise specified, V_CC = 9 V, Ta = 25 ± 3°C, data = preset values)
OFF B
ON
A
A (1) Input vertical trigger pulse to pin V_IN.
Pulse level (VT) = 3.0 V
(2) Set V-DF AMPLITUDE (sub-address: 06) to minimum (data: 80) and measure pin
18 (V-DF OUT) amplitude V_VD (80).
(3) Set V-DF AMPLITUDE (sub-address: 06) to center (data: 88) and measure pin 18
(V-DF OUT) amplitude V_VD (88).
(4) Set V-DF AMPLITUDE (sub-address: 06) to maximum (data: 8F) and measure pin
18 (V-DF OUT) amplitude V_VD (8F).
(5) Calculate change amounts V_VDP and V_VDN using the following formulas.
Pin 18 (V-DF OUT) waveform
V_VD (80) − V_VD (88)
V_VDP =
× 100
V_VD (88)
V_VD (8F) − V_VD (88)
V_VDN =
× 100
V_VD (88)
48
2002-09-06