TA1317AN Datasheet, PDF (11/59 Pages) Toshiba Semiconductor – TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic

Register Name/Number of Bits
V-EHT COMPENSATION/3
Function Explanation
Adjusts the compensated rate for the V-DRIVE by EHT-IN
(pin 3).
000: min
111: max
Output Change
Pin 6
Picture Change
TA1317AN
Preset
Solid line
Dashed line
min
(000)
ANALOG V-BLK STOP PHASE/5
Sets the analog blanking stop phase on pin 20. Inputs the
output from pin 20 to an external BLK-IN of synchronization
IC.
00000: min
10000: center
11111: max

Solid line
Dashed line
center
(10000)
H-EHT COMPENSATION/3
Adjusts the compensated rate for the EW output by EHT-IN
(pin 3).
000: min
111: max
Pin 11
Solid line
Dashed line
min
(000)
ANALOG V-BLK START PHASE/5
Sets the analog blanking start phase on pin 20. Inputs the
output from pin 20 to external BLK-IN of synchronization IC.
00000: min
10000: center
11111: max

Solid line
Dashed line
center
(10000)
V-RAMP LIMIT LEVEL/4
Sets the V-ramp slice level.
0000: OFF
0001: min
1111: max
Sub-address 05-D0 bit comes MSB.
Pin 6
OFF

(0000)
11
2002-09-06