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TA1317AN Datasheet, PDF (22/59 Pages) Toshiba Semiconductor – TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic
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Characteristics
AGC operating current
Sawtooth correction (cent saw)
maximum amplitude
Parabola correction (cent par)
maximum amplitude
Horizontal DF amplitude adjustment
(H DF amp)
Horizontal DF phase adjustment
(H DF phase)
Horizontal DF bathtub (H DF curve)
adjustment
Vertical DF amplitude adjustment
(V DF amp)
Vertical DF phase adjustment
(V DF phase)
LVP detection voltage
Vertical guard detection voltage
Vertical guard detection output current
(BLK-OUT output current)
Vertical centering DAC output voltage
1 (V centering)
Vertical centering DAC output voltage
2 (V shift)
Vertical centering change amount in V
STOP mode
Vertical NF signal amplitude at DC
coupling
Vertical NF center voltage at DC
coupling
Symbol
VX (00)
VX (40)
VX (80)
VX (C0)
VN (8F)
VN (80)
VP (F8)
VP (08)
VHD (80)
VHD (88)
VHD (8F)
VHDP
VHDN
THD (08)
THD (F8)
THD
THB (00)
THB (F0)
THB
VVD (80)
VVD (88)
VVD (8F)
VVDP
VVDN
TVD (08)
TVD (F8)
TVD
VLVP
VVGH
VVGL
I20
VCA (00)
VCA (FE)
VCD (80)
VCD (83)
VY (00)
VY (80)
VY (FE)
VDFB
VC
Test
Circuit
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TA1317AN
Test Condition
Min Typ. Max Unit
20
35
50
45
65
85
(Note 25)
µA
250 340 430
535 715 895
4.3 5.0 5.7
(Note 26)
Vp-p
4.3 5.0 5.7
1.9 2.2 2.5
(Note 27)
Vp-p
1.9 2.2 2.5
2.1 2.8 3.3
2.4
3.1
4.0 Vp-p
(Note 28) 2.6 3.4 4.3
7
10
13
%
−15 −12 −7
−6.0 −4.4 −2.0
(Note 29) 2.0
4.4
6.0 Vp-p
6.5 8.8 10.0
32.0 42.0 52.0
(Note 30) 21.0 31.0 41.0 µs
2.5 4.5 6.5
2.05 2.40 2.75
2.30 2.70 3.10 Vp-p
(Note 31) 2.55 3.00 3.45
7
10
13
%
−15 −10 −7
−2.5 −2.0 −1.5
(Note 32) 1.5 2.0 2.5 ms
3.4 4.0 4.6
(Note 33) 4.7 5.0 5.3
V
7.0 7.3 7.6
(Note 34)
V
2.1 2.4 2.7
(Note 35) 450 630 750 µA
0.20 0.50 0.55
(Note 36)
V
4.7 5.0 5.3
0.20 0.60 0.80
(Note 37)
V
4.7 5.0 5.3
1.7 1.9 2.1
(Note 38) 2.25 2.50 2.75
V
2.7 3.0 3.3
(Note 39) 0.85 0.95 1.05 Vp-p
(Note 40) 2.25 2.50 2.75
V
22
2002-09-06
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