MSP430F6779A Datasheet, PDF (84/176 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
www.ti.com
6.11.26 Embedded Emulation Module (EEM) (Link to User's Guide)
The Embedded Emulation Module (EEM) supports real-time in-system debugging. The L version of the
EEM implemented on all devices has the following features:
• Eight hardware triggers or breakpoints on memory access
• Two hardware triggers or breakpoints on CPU register write access
• Up to ten hardware triggers can be combined to form complex triggers or breakpoints
• Two cycle counters
• Sequencer
• State storage
• Clock control on module level
6.11.27 Peripheral File Map
Table 6-21 shows the base address for each peripheral's registers. Table 6-22 through Table 6-64 show
the offset addresses for each register. For complete description of these registers, see the MSP430x5xx
and MSP430x6xx Family User's Guide (SLAU208).
Table 6-21. Peripherals
MODULE NAME
Special Functions (see Table 6-22)
PMM (see Table 6-23)
Flash Control (see Table 6-24)
CRC16 (see Table 6-25)
RAM Control (see Table 6-26)
Watchdog (see Table 6-27)
UCS (see Table 6-28)
SYS (see Table 6-29)
Shared Reference (see Table 6-30)
Port Mapping Control (see Table 6-31)
Port Mapping Port P2 (see Table 6-32)
Port Mapping Port P3 (see Table 6-33)
Port Mapping Port P4 (see Table 6-34)
Port P1, P2 (see Table 6-35)
Port P3, P4 (see Table 6-36)
Port P5, P6 (see Table 6-37)
Port P7, P8 (see Table 6-38)
Port P9, P10 (see Table 6-39)
(Ports P9 and P10 not available in PZ package)
Port P11 (see Table 6-40)
(Port P11 not available in PZ package)
Port PJ (see Table 6-41)
Timer TA0 (see Table 6-42)
Timer TA1 (see Table 6-43)
Timer TA2 (see Table 6-44)
Timer TA3 (see Table 6-45)
Backup Memory (see Table 6-46)
32-Bit Hardware Multiplier (see Table 6-48)
DMA General Control (see Table 6-49)
DMA Channel 0 (see Table 6-50)
BASE ADDRESS
0100h
0120h
0140h
0150h
0158h
015Ch
0160h
0180h
01B0h
01C0h
01D0h
01D8h
01E0h
0200h
0220h
0240h
0260h
0280h
02A0h
0320h
0340h
0380h
0400h
0440h
0480h
04C0h
0500h
0500h
OFFSET ADDRESS
RANGE
000h-01Fh
000h-01Fh
000h-00Fh
000h-007h
000h-001h
000h-001h
000h-01Fh
000h-01Fh
000h-001h
000h-007h
000h-007h
000h-007h
000h-007h
000h-01Fh
000h-00Bh
000h-00Bh
000h-00Bh
000h-00Bh
000h-00Bh
000h-01Fh
000h-03Fh
000h-03Fh
000h-03Fh
000h-03Fh
000h-00Fh
000h-02Fh
000h-00Fh
010h-01Fh
84
Detailed Description
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