MSP430F6779A Datasheet, PDF (24/176 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
TERMINAL
NAME
Table 4-4. Terminal Functions – PZ Package (continued)
NO. I/O⁽¹⁾
PZ
DESCRIPTION
P8.0/S0
93 I/O ^{General-purpose digital I/O}
LCD segment output S0
General-purpose digital I/O
P8.1/TACLK/RTCCLK/CB3 94 I/O ^{Timer clock input TACLK for TA0, TA1, TA2, TA3}
RTCCLK clock output
Comparator_B input CB3
TEST/SBWTCK
95
I ^{Test mode pin – select digital I/O on JTAG pins}
Spy-By-Wire input clock
PJ.0/TDO
96 I/O ^{General-purpose digital I/O}
Test data output
PJ.1/TDI/TCLK
97 I/O ^{General-purpose digital I/O}
Test data input or Test clock input
PJ.2/TMS
98 I/O ^{General-purpose digital I/O}
Test mode select
PJ.3/TCK
99 I/O ^{General-purpose digital I/O}
Test clock
RST/NMI/SBWTDIO
Reset input active low⁽⁶⁾
100 I/O _{Non-maskable interrupt input}
Spy-By-Wire data input/output
(6) When this pin is configured as reset, the internal pullup resistor is enabled by default.
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Terminal Configuration and Functions
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A