MSP430F6779A Datasheet, PDF (62/176 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
www.ti.com
5.8.12 Flash
Table 5-53. Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP MAX UNIT
DV_{CC(PGM/ERASE)}
I_PGM
I_ERASE
I_MERASE,
I_BANK
t_CPT
Program and erase supply voltage
Average supply current from DVCC during program
Average supply current from DVCC during erase
Average supply current from DVCC during mass erase or
bank erase
Cumulative program time
Program and erase endurance
See ⁽¹⁾
1.8
3.6 V
3
5 mA
6
15 mA
6
15 mA
10⁴
10⁵
16 ms
cycles
t_Retention
t_Word
t_{Block, 0}
Data retention duration
Word or byte program time
Block program time for first byte or word
T_J = 25°C
100
See ⁽²⁾
64
See ⁽²⁾
49
t_{Block, 1–(N–1)}
Block program time for each additional byte or word,
except for last byte or word
See ⁽²⁾
37
t_{Block, N}
Block program time for last byte or word
See ⁽²⁾
55
t_Erase
Erase time for segment erase, mass erase, and bank
erase when available
See ⁽²⁾
23
years
85 µs
65 µs
49 µs
73 µs
32 ms
f_MCLK,MGR
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
0
1 MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
(2) These values are hardwired into the flash controller's state machine.
5.9 Emulation and Debug
Table 5-54. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP
f_SBW
t_SBW,Low
t_{SBW, En}
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse duration
Spy-Bi-Wire enable time (TEST high to acceptance of first
clock edge)⁽¹⁾
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
0
0.025
t_SBW,Rst
f_TCK
Spy-Bi-Wire return to normal operation time
TCK input frequency for 4-wire JTAG⁽²⁾
15
2.2 V
0
3V
0
R_internal
Internal pulldown resistance on TEST
2.2 V, 3 V
45
60
MAX UNIT
20 MHz
15 µs
1 µs
100 µs
5 MHz
10 MHz
80 kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the minimum t_SBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
(2) f_TCK may be restricted to meet the timing requirements of the module selected.
62
Specifications
Copyright © 2014, Texas Instruments Incorporated
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A