MSP430F6779A Datasheet, PDF (64/176 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
www.ti.com
6.2 Functional Block Diagrams
Figure 6-1 shows the the functional block diagram for the MSP430F677xA, MSP430F676xA, and
MSP430F674xA devices in the PEU package.
XIN XOUT
(32 kHz)
DVCC DVSS AVCC AVSS AUX1 AUX2 AUX3 RST/NMI
PA
P1.x P2.x
PB
P3.x P4.x
PC
PD
P5.x P6.x P7.x P8.x
PE
P9.x P10.x
PF
P11.x
Unified
Clock
System
ACLK
SMCLK
MCLK
512KB
256KB
128KB
Flash
CPUXV2
and
Working
Registers
(25 MHz)
32KB
16KB
RAM
SYS
Watchdog
Port
Mapping
Controller
CRC16
MPY32
AES128
I/O Ports
P1, P2
2×8 I/Os
Interrupt,
Wakeup
PA
1×16 I/Os
I/O Ports
P3, P4
2×8 I/Os
PB
1×16 I/Os
I/O Ports
P5, P6
2×8 I/Os
PC
1×16 I/Os
I/O Ports
P7, P8
2×8 I/Os
PD
1×16 I/Os
I/O Ports
P9, P10
2×8 I/O
PE
1×16 I/O
I/O Ports
P11
1×6 I/O
PF
1×6 I/O
PJ.x
EEM
(S: 8+2)
JTAG.
SBW
Interface
Port PJ
PMM
Auxiliary
Supplies
LDO
SVM, SVS
BOR
SD24_B
7 Channel
6 Channel
4 Channel
ADC10_A
LCD_C
REF
10 Bit
200 KSPS
8MUX
Up to 320
Segments
Reference
1.5 V, 2.0 V,
2.5 V
RTC_CE
Ta0
Timer_A
3 CC
Registers
TA1
TA2
TA3
Timer_A
2 CC
Registers
eUSCI_A0
eUSCI_A1
eUSCI_A2
eUSCI_A3
(UART,
IrDA,SPI)
eUSCI_B0
eUSCI_B1
(SPI, I²C)
DMA
3 Channel
COMP_B
(External
Voltage
Monitoring)
Figure 6-1. Functional Block Diagram – PEU Package
Figure 6-2 shows the the functional block diagram for the MSP430F677xA, MSP430F676xA, and
MSP430F674xA devices in the PZ package.
XIN XOUT
(32 kHz)
DVCC DVSS AVCC AVSS AUX1 AUX2 AUX3 RST/NMI
PA
P1.x P2.x
PB
P3.x P4.x
PC
PD
P5.x P6.x P7.x P8.x
Unified
Clock
System
ACLK
SMCLK
MCLK
512KB
256KB
128KB
Flash
CPUXV2
and
Working
Registers
(25 MHz)
32KB
16KB
RAM
SYS
Watchdog
Port
Mapping
Controller
CRC16
MPY32
AES128
I/O Ports
P1, P2
2×8 I/Os
Interrupt,
Wakeup
PA
1×16 I/Os
I/O Ports
P3, P4
2×8 I/Os
PB
1×16 I/Os
I/O Ports
P5, P6
2×8 I/Os
PC
1×16 I/Os
I/O Ports
P7, P8
1×8 I/Os
1×2 I/Os
PD
1×10 I/Os
PJ.x
EEM
(S: 8+2)
JTAG,
SBW
Interface
Port PJ
PMM
Auxiliary
Supplies
LDO
SVM, SVS
BOR
SD24_B
7 Channel
6 Channel
4 Channel
ADC10_A
LCD_C
REF
10 Bit
200 KSPS
8MUX
Up to 320
Segments
Reference
1.5 V, 2.0 V,
2.5 V
RTC_CE
Ta0
Timer_A
3 CC
Registers
TA1
TA2
TA3
Timer_A
2 CC
Registers
eUSCI_A0
eUSCI_A1
eUSCI_A2
eUSCI_A3
(UART,
IrDA,SPI)
eUSCI_B0
eUSCI_B1
(SPI, I²C)
DMA
3 Channel
COMP_B
(External
Voltage
Monitoring)
Figure 6-2. Functional Block Diagram – PZ Package
64
Detailed Description
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