MSP430F6779A Datasheet, PDF (44/176 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
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f_eUSCI
Table 5-29. eUSCI (SPI Master Mode), Recommended Operating Conditions
PARAMETER
eUSCI input clock frequency
CONDITIONS
Internal: SMCLK or ACLK,
Duty cycle = 50% ± 10%
V_CC
MIN TYP MAX UNIT
f_SYSTEM MHz
Table 5-30. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
PARAMETER
t_STE,LEAD STE lead time, STE low to clock
TEST CONDITIONS
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
V_CC
2 V, 3 V
2 V, 3 V
MIN TYP
150
150
MAX UNIT
ns
UCSTEM = 0, UCMODEx = 01 or 10 2 V, 3 V
200
t_STE,LAG
STE lag time, Last clock to STE high
UCSTEM = 1, UCMODEx = 01 or 10
2 V, 3 V
200
ns
2V
UCSTEM = 0, UCMODEx = 01 or 10
t_STE,ACC
STE access time, STE low to SIMO
data out
3V
2V
UCSTEM = 1, UCMODEx = 01 or 10
3V
50
30
ns
50
30
2V
UCSTEM = 0, UCMODEx = 01 or 10
t_STE,DIS
STE disable time, STE high to SIMO
high impedance
3V
2V
UCSTEM = 1, UCMODEx = 01 or 10
3V
40
25
ns
40
25
t_SU,MI
SOMI input data setup time
2V
50
ns
3V
30
t_HD,MI
SOMI input data hold time
2V
0
ns
3V
0
t_VALID,MO SIMO output data valid time⁽²⁾
2V
UCLK edge to SIMO valid, C_L = 20 pF
3V
9
ns
5
t_HD,MO
SIMO output data hold time⁽³⁾
C_L = 20 pF
2V
0
ns
3V
0
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI = max(t_{VALID,MO(eUSCI)} + t_SU,SI(Slave), t_SU,MI(eUSCI) + t_{VALID,SO(Slave)}).
For the slave's parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)} see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-11 and Figure 5-12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
11 and Figure 5-12.
44
Specifications
Copyright © 2014, Texas Instruments Incorporated
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A