MSP430F6779A Datasheet, PDF (69/176 Pages) Texas Instruments – Polyphase Metering SoCs

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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
Table 6-3. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
Reserved
INTERRUPT FLAG
Reserved ⁽⁵⁾
SYSTEM INTERRUPT
WORD
ADDRESS
0FFC6h
⋮
0FF80h
PRIORITY
35
⋮
0, lowest
(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
6.7 Special Function Registers (SFRs)
The MSP430 SFRs are located in the lowest address space and can be accessed via word or byte
formats.
Legend
rw:
rw-0,1:
rw-(0,1):
rw-[0,1]:
–
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
Bit can be read and written. It is reset or set by BOR.
SFR bit is not present in device.
Table 6-4. Interrupt Enable 1
15
–
7
JMBOUTIE
rw-0
WDTIE
OFIE
VMAIE
NMIIE
ACCVIE
JMBINIE
JMBOUTIE
AUXSWNMIE
14
–
6
JMBINIE
rw-0
13
–
5
ACCVIE
rw-0
12
–
4
NMIIE
rw-0
11
–
3
VMAIE
rw-0
10
9
8
–
AUXSWNMIE
–
rw-0
2
1
0
–
OFIE
WDTIE
rw-0
rw-0
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured as a
general-purpose timer.
Oscillator fault interrupt enable
Vacant memory access interrupt enable
Nonmaskable interrupt enable
Flash access violation interrupt enable
JTAG mailbox input interrupt enable
JTAG mailbox output interrupt enable
Supply switched non-maskable interrupt enable
Table 6-5. Interrupt Flag 1
15
–
7
JMBOUTIFG
rw-[0]
WDTIFG
OFIFG
VMAIFG
NMIIFG
JMBINIFG
JMBOUTIFG
14
13
12
11
10
–
–
–
–
–
6
5
JMBINIFG
–
rw-[0]
4
3
2
NMIIFG
VMAIFG
–
rw-0
rw-0
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on V_CC power-on or a reset condition at the RST/NMI pin in reset mode
Flag set on oscillator fault
Set on vacant memory access
Set via RST/NMI pin
Set on JTAG mailbox input message
Set on JTAG mailbox output register ready for next message
9
–
1
OFIFG
rw-0
8
–
0
WDTIFG
rw-0
Copyright © 2014, Texas Instruments Incorporated
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A