MSP430F6779A Datasheet, PDF (68/176 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
www.ti.com
6.6 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
System Reset
Power-Up
External Reset
Watchdog Timeout, Key Violation
Flash Memory Key Violation
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
Supply Switched
Watchdog Timer_A Interval Timer
Mode
eUSCI_A0 Receive or Transmit
eUSCI_B0 Receive or Transmit
ADC10_A
SD24_B
Timer TA0
Timer TA0
eUSCI_A1 Receive or Transmit
eUSCI_A2 Receive or Transmit
Auxiliary Supplies
DMA
Timer TA1
Timer TA1
eUSCI_A3 Receive or Transmit
eUSCI_B1 Receive or Transmit
I/O Port P1
Timer TA2
Timer TA2
I/O Port P2
Timer TA3
Timer TA3
LCD_C
RTC_C
Comparator_B
AES
Table 6-3. Interrupt Sources, Flags, and Vectors
INTERRUPT FLAG
SYSTEM INTERRUPT
WDTIFG, KEYV (SYSRSTIV)^{(1) (2)}
Reset
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG,
VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)
(1) (3)
(Non)maskable
NMIIFG, OFIFG, ACCVIFG, AUXSWGIFG (SYSUNIV) ⁽¹⁾
(3)
(Non)maskable
WDTIFG
UCA0RXIFG, UCA0TXIFG (UCA0IV) ^{(1) (4)}
UCB0RXIFG, UCB0TXIFG (UCB0IV) ^{(1) (4)}
ADC10IFG0, ADC10INIFG, ADC10LOIFG, ADC10HIIFG,
ADC10TOVIFG, ADC10OVIFG (ADC10IV)^{(1) (4)}
SD24_B Interrupt Flags (SD24IV)^{(1) (4)}
TA0CCR0 CCIFG0⁽⁴⁾
TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,
TA0IFG (TA0IV) ^{(1) (4)}
UCA1RXIFG, UCA1TXIFG (UCA1IV) ^{(1) (4)}
UCA2RXIFG, UCA2TXIFG (UCA2IV) ^{(1) (4)}
AUXSWGIFG, AUXIFG0, AUXIFG1, AUXIFG2
(AUXIV)^{(1) (4)}
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)^{(1) (4)}
TA1CCR0 CCIFG0⁽⁴⁾
TA1CCR1 CCIFG1,
TA1IFG (TA1IV) ^{(1) (4)}
UCA3RXIFG, UCA3TXIFG (UCA3IV) ^{(1) (4)}
UCB1RXIFG, UCB1TXIFG (UCB1IV) ^{(1) (4)}
P1IFG.0 to P1IFG.7 (P1IV) ^{(1) (4)}
TA2CCR0 CCIFG0⁽⁴⁾
TA2CCR1 CCIFG1,
TA2IFG (TA2IV) ^{(1) (4)}
P2IFG.0 to P2IFG.7 (P2IV) ^{(1) (4)}
TA3CCR0 CCIFG0⁽⁴⁾
TA3CCR1 CCIFG1,
TA3IFG (TA3IV) ^{(1) (4)}
LCD_C Interrupt Flags (LCDCIV)^{(1) (4)}
RTCOFIFG, RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG (RTCIV)^{(1) (4)}
Comparator_B Interrupt Flags (CBIV) ⁽¹⁾
AESRDYIFG
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
WORD
ADDRESS
0FFFEh
0FFFCh
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
0FFEAh
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
0FFDEh
0FFDCh
0FFDAh
0FFD8h
0FFD6h
0FFD4h
0FFD2h
0FFD0h
0FFCEh
0FFCCh
0FFCAh
0FFC8h
PRIORITY
63, highest
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(4) Interrupt flags are located in the module.
68
Detailed Description
Copyright © 2014, Texas Instruments Incorporated
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