MSP430F6779A Datasheet, PDF (48/176 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
www.ti.com
Table 5-32. eUSCI (I²C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-15)
f_eUSCI
PARAMETER
eUSCI input clock frequency
TEST CONDITIONS
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
V_CC
MIN TYP MAX UNIT
f_SYSTEM MHz
f_SCL
t_HD,STA
t_SU,STA
t_HD,DAT
t_SU,DAT
t_SU,STO
SCL clock frequency
Hold time (repeated) START
Setup time for a repeated START
Data hold time
Data setup time
Setup time for STOP
f_SCL = 100 kHz
f_SCL > 100 kHz
f_SCL = 100 kHz
f_SCL > 100 kHz
f_SCL = 100 kHz
f_SCL > 100 kHz
f_SCL = 100 kHz
f_SCL > 100 kHz
UCGLITx = 0
2 V, 3 V
0
5.1
2 V, 3 V
1.5
5.1
2 V, 3 V
1.4
2 V, 3 V
0.4
5.0
2 V, 3 V
1.3
5.2
2 V, 3 V
1.7
75
400 kHz
µs
µs
µs
µs
µs
220 ns
t_SP
Pulse duration of spikes suppressed by input ^{UCGLITx = 1}
filter
UCGLITx = 2
35
2 V, 3 V
30
120 ns
60 ns
UCGLITx = 3
20
35 ns
UCCLTOx = 1
30
ms
t_TIMEOUT Clock low timeout
UCCLTOx = 2
UCCLTOx = 3
2 V, 3 V
33
ms
37
ms
SDA
t_HD,STA
t_SU,STA
t_HD,STA
t_BUF
t_LOW
t_HIGH
t_SP
SCL
t_HD,DAT
t_SU,DAT
Figure 5-15. I²C Mode Timing
t_SU,STO
48
Specifications
Copyright © 2014, Texas Instruments Incorporated
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