MSP430F6779A Datasheet, PDF (46/176 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
www.ti.com
Table 5-31. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
PARAMETER
t_STE,LEAD STE lead time, STE low to clock
TEST CONDITIONS
V_CC
MIN TYP MAX UNIT
2V
4
ns
3V
3
t_STE,LAG STE lag time, Last clock to STE high
2V
0
ns
3V
0
t_STE,ACC STE access time, STE low to SOMI data out
2V
46
ns
3V
24
t_STE,DIS
STE disable time, STE high to SOMI high
impedance
2V
38
ns
3V
25
t_SU,SI
SIMO input data setup time
2V
2
ns
3V
1
t_HD,SI
SIMO input data hold time
2V
2
ns
3V
2
t_VALID,SO SOMI output data valid time⁽²⁾
UCLK edge to SOMI valid,
2V
C_L = 20 pF
3V
55
ns
32
t_HD,SO
SOMI output data hold time⁽³⁾
C_L = 20 pF
2V
24
ns
3V
16
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(eUSCI), t_{SU,MI(Master)} + t_{VALID,SO(eUSCI)}).
For the master's parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)} refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-13 and Figure 5-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13
and Figure 5-14.
UCMODEx = 01
STE
UCMODEx = 10
CKPL = 0
UCLK
CKPL = 1
SIMO
t_STE,LEAD
1/f_UCxCLK
t_LOW/HIGH
t_LOW/HIGH
t_STE,LAG
t_SU,SIMO
t_HD,SIMO
SOMI
t_ACC
t_VALID,SOMI
t_DIS
Figure 5-13. SPI Slave Mode, CKPH = 0
46
Specifications
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