MSP430F6779A Datasheet, PDF (59/176 Pages) Texas Instruments – Polyphase Metering SoCs

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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
Table 5-49. 10-Bit ADC Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
E_I
Integral
linearity error
E_D
Differential
linearity error
E_O
Offset error
E_G
Gain error
E_T
Total unadjusted
error
TEST CONDITIONS
1.4 V ≤ (V_eREF+ – V_REF–/V_eREF–)min ≤ 1.6 V
1.6 V < (V_eREF+ – V_REF–/V_eREF–)min ≤ V_AVCC
(V_eREF+ – V_REF–/V_eREF–)min ≤ (V_eREF+ – V_REF–/V_eREF–),
C_VREF+ = 20 pF
(V_eREF+ – V_REF–/V_eREF–)min ≤ (V_eREF+ – V_REF–/V_eREF–),
Internal impedance of source R_S < 100 Ω, C_VREF+ = 20 pF
(V_eREF+ – V_REF–/V_eREF–)min ≤ (V_eREF+ – V_REF–/V_eREF–),
C_VREF+ = 20 pF
(V_eREF+ – V_REF–/V_eREF–)min ≤ (V_eREF+ – V_REF–/V_eREF–),
C_VREF+ = 20 pF
V_CC
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
MIN TYP
-1.0
-1.0
-1.0
-1.0
-1.0
-2.0
MAX
+1.0
+1.0
UNIT
LSB
+1.0 LSB
+1.0 LSB
+1.0 LSB
+2.0 LSB
Table 5-50. 10-Bit ADC External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
V_eREF+
PARAMETER
TEST CONDITIONS
Positive external reference
voltage input
V_eREF+ > V_REF–/V_eREF– ⁽²⁾
V_CC
MIN TYP MAX UNIT
1.4
AV_CC V
V_eREF–
Negative external
reference voltage input
V_eREF+ > V_REF–/V_eREF– ⁽³⁾
0
1.2 V
(V_eREF+ –
V_eREF–)
I_VeREF+
I_VeREF–
Differential external
reference voltage input
Static input current
V_eREF+ > V_REF–/V_eREF– ⁽⁴⁾
1.4 V ≤ V_eREF+ ≤ V_AVCC , V_eREF– = 0 V,
f_ADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
Conversion rate 200 ksps
1.4 V ≤ V_eREF+ ≤ V_AVCC , V_eREF– = 0 V,
f_ADC10CLK = 5 MHZ, ADC10SHTX = 0x1000,
Conversion rate 20 ksps
1.4
2.2 V, 3 V
-26
2.2 V, 3 V
-1
AV_CC V
+26 µA
+1 µA
C_VREF+
Capacitance at VREF+
terminal
(5)₁₀
µF
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, C_I, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
Copyright © 2014, Texas Instruments Incorporated
Specifications
59
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