MSP430F6779A Datasheet, PDF (77/176 Pages) Texas Instruments – Polyphase Metering SoCs

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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
Table 6-11. Port Mapping Mnemonics and Functions (continued)
VALUE
21
22
23
24
25
26
27
28
29
30
31 (0FFh) ⁽¹⁾
PxMAPy MNEMONIC
PM_UCB1SIMO
PM_UCB1SDA
PM_UCB1SOMI
PM_UCB1SCL
PM_UCB1CLK
PM_UCB1STE
PM_TA0.0
PM_TA0.1
PM_TA0.2
PM_TA1.0
PM_TA2.0
PM_TA3.0
PM_ANALOG
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
eUSCI_B1 SPI slave in master out (direction controlled by eUSCI)
eUSCI_B1 I2C data (open drain and direction controlled by eUSCI)
eUSCI_B1 SPI slave out master in (direction controlled by eUSCI)
eUSCI_B1 I2C clock (open drain and direction controlled by eUSCI)
eUSCI_B1 clock input/output (direction controlled by eUSCI)
eUSCI_B1 SPI slave transmit enable (direction controlled by eUSCI)
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
TA1 CCR0 capture input CCI0A
TA1 CCR0 compare output Out0
TA2 CCR0 capture input CCI0A
TA2 CCR0 compare output Out0
TA3 CCR0 capture input CCI0A
TA3 CCR0 compare output Out0
Disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored,
which results in a read value of 31.
Table 6-12. Default Port Mapping
PIN NAME
PEU
PZ
P2.0/PM_TA0.0
P2.0/PM_TA0.0/COM4
P2.1/PM_TA0.1
P2.1/PM_TA0.1/COM5
P2.2/PM_TA0.2
P2.2/PM_TA0.2/COM6
P2.3/PM_TA1.0
P2.3/PM_TA1.0/COM7
P2.4/PM_TA2.0
P1.1/PM_TA2.0/R23
P2.5/PM_UCB0SOMI/
PM_UCB0SCL
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/R13
P2.6/PM_UCB0SIMO/
PM_UCB0SDA
P2.6/PM_UCB0SIMO/
PM_UCB0SDA/R03
P2.7/PM_UCB0CLK
P2.7/PM_UCB0CLK/CB2
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
P3.1/PM_UCA0TXD/
PM_UCA0SIMO
P3.1/PM_UCA0TXD/
PM_UCA0SIMO/S39
P3.2/PM_UCA0CLK
P3.2/PM_UCA0CLK/S38
P3.3/PM_UCA1CLK
P3.3/PM_UCA1CLK/S37
P3.4/PM_UCA1RXD/
PM_UCA1SOMI/
P3.4/PM_UCA1RXD/
PM_UCA1SOMI/S36
P3.5/PM_UCA1TXD/
PM_UCA1SIMO
P3.5/PM_UCA1TXD/
PM_UCA1SIMO/S35
P3.6/PM_UCA2RXD/
PM_UCA2SOMI/
P3.6/PM_UCA2RXD/
PM_UCA2SOMI/S34
P3.7/PM_UCA2TXD/
PM_UCA2SIMO
P3.7/PM_UCA2TXD/
PM_UCA2SIMO/S33
P4.0/PM_UCA2CLK
P4.0/PM_UCA2CLK/S32
P4.1/PM_UCA3RXD/
PM_UCA3SOMI/
P4.1/PM_UCA3RXD/
PM_UCA3SOMI/S31
P4.2/PM_UCA3TXD/
PM_UCA3SIMO
P4.2/PM_UCA3TXD/
PM_UCA3SIMO/S30
P4.3/PM_UCA3CLK
P4.3/PM_UCA3CLK/S29
P4.4/PM_UCB1SOMI/
PM_UCB1SCL
P4.4/PM_UCB1SOMI/
PM_UCB1SCL/S28
P4.5/PM_UCB1SIMO/
PM_UCB1SDA
P4.5/PM_UCB1SIMO/
PM_UCB1SDA/S27
P4.6/PM_UCB1CLK
P4.6/PM_UCB1CLK/S26
P4.7/PM_TA3.0
P4.7/PM_TA3.0/S25
PxMAPy
MNEMONIC
PM_TA0.0
PM_TA0.1
PM_TA0.2
PM_TA1.0
PM_TA2.0
PM_UCB0SOMI/
PM_UCB0SCL
PM_UCB0SIMO/
PM_UCB0SDA
PM_UCB0CLK
PM_UCA0RXD/
PM_UCA0SOMI
PM_UCA0TXD/
PM_UCA0SIMO
PM_UCA0CLK
PM_UCA1CLK
PM_UCA1RXD/
PM_UCA1SOMI
PM_UCA1TXD/
PM_UCA1SIMO
PM_UCA2RXD/
PM_UCA2SOMI
PM_UCA2TXD/
PM_UCA2SIMO
PM_UCA2CLK
PM_UCA3RXD/
PM_UCA3SOMI
PM_UCA3TXD/
PM_UCA3SIMO
PM_UCA3CLK
PM_UCB1SOMI/
PM_UCB1SCL
PM_UCB1SIMO/
PM_UCB1SDA
PM_UCB1CLK
PM_TA3.0
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
TA1 CCR0 capture input CCI0A
TA1 CCR0 compare output Out0
TA2 CCR0 capture input CCI0A
TA2 CCR0 compare output Out0
eUSCI_B0 SPI slave out master in (direction controlled by eUSCI),
eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
eUSCI_B0 SPI slave in master out (direction controlled by eUSCI),
eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
eUSCI_B0 clock input/output (direction controlled by eUSCI)
eUSCI_A0 UART RXD (direction controlled by eUSCI – input),
eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A0 UART TXD (direction controlled by eUSCI – output),
eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A0 clock input/output (direction controlled by eUSCI)
eUSCI_A1 clock input/output (direction controlled by eUSCI)
eUSCI_A1 UART RXD (direction controlled by eUSCI – input),
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A1 UART TXD (direction controlled by eUSCI – output),
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A2 UART RXD (direction controlled by eUSCI – input),
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A2 UART TXD (direction controlled by eUSCI – output),
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A2 clock input/output (direction controlled by eUSCI)
eUSCI_A3 UART RXD (direction controlled by eUSCI – input),
eUSCI_A3 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A3 UART TXD (direction controlled by eUSCI – output),
eUSCI_A3 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A3 clock input/output (direction controlled by eUSCI)
eUSCI_B1 SPI slave out master in (direction controlled by eUSCI),
eUSCI_B1 I2C clock (open drain and direction controlled by eUSCI)
eUSCI_B1 SPI slave in master out (direction controlled by eUSCI),
eUSCI_B1 I2C data (open drain and direction controlled by eUSCI)
eUSCI_B1 clock input/output (direction controlled by eUSCI)
TA3 CCR0 capture input CCI0A
TA3 CCR0 compare output Out0
Copyright © 2014, Texas Instruments Incorporated
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A