MSP430F6779A Datasheet, PDF (6/176 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
www.ti.com
4 Terminal Configuration and Functions
4.1 Pin Diagrams
The following figures show the pin diagrams for the MSP430F677xA, MSP430F676xA, and
MSP430F674xA devices.
XIN
XOUT
AUXVCC3
RTCCAP1
RTCCAP0
P1.5/SMCLK/CB0/A5
P1.4/MCLK/CB1/A4
P1.3/ADC10CLK/A3
P1.2/ACLK/A2
P1.1/TA2.1/VeREF+/A1
P1.0/TA1.1/VeREF-/A0
P2.4/PM_TA2.0
P2.5/PM_UCB0SOMI/PM_UCB0SCL
P2.6/PM_UCB0SIMO/PM_UCB0SDA
P2.7/PM_UCB0CLK
P3.0/PM_UCA0RXD/PM_UCA0SOMI
P3.1/PM_UCA0TXD/PM_UCA0SIMO
P3.2/PM_UCA0CLK
P3.3/PM_UCA1CLK
P3.4/PM_UCA1RXD/PM_UCA1SOMI
P3.5/PM_UCA1TXD/PM_UCA1SIMO
COM0
COM1
P1.6/COM2
P1.7/COM3
P5.0/COM4
P5.1/COM5
P5.2/COM6
P5.3/COM7
LCDCAP/R33
P5.4/SDCLK/R23
P5.5/SD0DIO/LCDREF/R13
P5.6/SD1DIO/R03
P5.7/SD2DIO/CB2
P6.0/SD3DIO
P3.6/PM_UCA2RXD/PM_UCA2SOMI
P3.7/PM_UCA2TXD/PM_UCA2SIMO
P4.0/PM_UCA2CLK
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
1
102
2
101
3
100
4
99
5
98
6
97
7
96
8
95
9
94
10
93
11
92
12
91
13
90
14
89
15
88
16
87
17
86
18
85
19
84
PEU PACKAGE
20
83
21
82
22
81
23
80
24
79
25
78
26
77
27
76
28
75
29
74
30
73
31
72
32
71
33
70
34
69
35
68
36
67
37
66
38
65
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P2.3/PM_TA1.0
P2.2/PM_TA0.2
P2.1/PM_TA0.1/BSL_RX
P2.0/PM_TA0.0/BSL_TX
P11.5/TACLK/RTCCLK
P11.4/CBOUT
P11.3/TA2.1
P11.2/TA1.1
P11.1/TA3.1/CB3
P11.0/S0
P10.7/S1
P10.6/S2
P10.5/S3
P10.4/S4
P10.3/S5
P10.2/S6
P10.1/S7
P10.0/S8
P9.7/S9
P9.6/S10
P9.5/S11
P9.4/S12
P9.3/S13
P9.2/S14
P9.1/S15
P9.0/S16
DVSS2
VDSYS2
P8.7/S17
P8.6/S18
P8.5/S19
P8.4/S20
A. The secondary digital functions on Ports P2, P3 and P4 are fully mappable. The pin designation shows only the
default mapping. See Table 6-11 for details.
B. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on board for proper
device operation.
C. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used.
Figure 4-1. 128-Pin PEU Package (Top View)
6
Terminal Configuration and Functions
Copyright © 2014, Texas Instruments Incorporated
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A