MSP430F6779A Datasheet, PDF (16/176 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
www.ti.com
TERMINAL
NAME
P11.5/TACLK/RTCCLK
P2.0/PM_TA0.0/BSL_TX
P2.1/PM_TA0.1/BSL_RX
P2.2/PM_TA0.2
P2.3/PM_TA1.0
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
RST/NMI/SBWTDIO
SD0P0
SD0N0
SD1P0
SD1N0
SD2P0
SD2N0
SD3P0
Table 4-3. Terminal Functions – PEU Package (continued)
NO. I/O⁽¹⁾
PEU
DESCRIPTION
General-purpose digital I/O
92 I/O _{Timer clock input TACLK for TA0, TA1, TA2, TA3}
RTCCLK clock output
General-purpose digital I/O with port interrupt and mappable secondary function
93 I/O _{Default mapping: Timer TA0 capture CCR0: CCI0A input, compare: Out0 output}
Bootstrap loader: Data transmit
General-purpose digital I/O with port interrupt and mappable secondary function
94 I/O _{Default mapping: Timer TA0 capture CCR1: CCI1A input, compare: Out1 output}
Bootstrap loader: Data receive
95 I/O ^{General-purpose digital I/O with port interrupt and mappable secondary function}
Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output
96 I/O ^{General-purpose digital I/O port interrupt and with mappable secondary function}
Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
97
I ^{Test mode pin – select digital I/O on JTAG pins}
Spy-Bi-Wire input clock
98 I/O ^{General-purpose digital I/O}
Test data output
99 I/O ^{General-purpose digital I/O}
Test data input or Test clock input
100 I/O ^{General-purpose digital I/O}
Test mode select
101 I/O ^{General-purpose digital I/O}
Test clock
Reset input active low⁽³⁾
102 I/O _{Non-maskable interrupt input}
Spy-By-Wire data input/output
103 I _{SD24_B positive analog input for converter 0}(4)
104 I _{SD24_B negative analog input for converter 0}(4)
105 I _{SD24_B positive analog input for converter 1}(4)
106 I _{SD24_B negative analog input for converter 1}(4)
107 I _{SD24_B positive analog input for converter 2}(4)
108 I _{SD24_B negative analog input for converter 2}(4)
109 I _{SD24_B positive analog input for converter 3}(4)
(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(4) It is recommended to short unused analog input pairs and connect them to analog ground.
16
Terminal Configuration and Functions
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Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A