MSP430F6779A Datasheet, PDF (8/176 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
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SD0P0
SD0N0
SD1P0
SD1N0
SD2P0
SD2N0
SD3P0
SD3N0
VASYS2
AVSS2
VREF
SD4P0
SD4N0
SD5P0
SD5N0
SD6P0
SD6N0
AVSS1
AVCC
VASYS1
AUXVCC2
AUXVCC1
VDSYS1
DVCC
DVSS1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
66
11
65
12
64
13
PZ PACKAGE
63
14
62
15
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VDSYS2
P5.7/SD6DIO/S17
P5.6/SD5DIO/S18
P5.5/SD4DIO/S19
P5.4/SD3DIO/S20
P5.3/SD2DIO/S21
P5.2/SD1DIO/S22
P5.1/SD0DIO/S23
P5.0/SDCLK/S24
P4.7/PM_TA3.0/S25
P4.6/PM_UCB1CLK/S26
P4.5/PM_UCB1SIMO/PM_UCB1SDA/S27
P4.4/PM_UCB1SOMI/PM_UCB1SCL/S28
P4.3/PM_UCA3CLK/S29
P4.4/PM_UCA3TXD/PM_UCA3SIMO/S30
P4.1/PM_UCA3RXD/PM_UCA3SOMI/S31
P4.0/PM_UCA2CLK/S32
P3.7/PM_UCA2TXD/PM_UCA2SIMO/S33
P3.6/PM_UCA2RXD/PM_UCA2SOMI/S34
P3.5/PM_UCA1TXD/PM_UCA1SIMO/S35
P3.4/PM_UCA1RXD/PM_UCA1SOMI/S36
P3.3/PM_UCA1CLK/S37
P3.2/PM_UCA0CLK/S38
P3.1/PM_UCA0TXD/PM_UCA0SIMO/S39
P3.0/PM_UCA0RXD/PM_UCA0SOMI
A. The secondary digital functions on Ports P2, P3 and P4 are fully mappable. The pin designation shows only the
default mapping. See Table 6-11 for details.
B. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on board for proper
device operation.
C. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used.
Figure 4-2. 100-Pin PZ Package (Top View)
8
Terminal Configuration and Functions
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A