MSP430F6779A Datasheet, PDF (76/176 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
www.ti.com
6.11.5 Digital I/O (Link to User's Guide)
There are up to eleven 8-bit I/O ports implemented. For 128-pin options, Ports P1 to P10 are complete,
and Port P11 is 6 bits wide. For 100-pin options, Ports P1 to P7 are complete, Port P8 is 2 bits wide, and
ports P9, P10, and P11 are completely removed. Port PJ contains four individual I/O pins, common to all
devices. All I/O bits are individually programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Programmable drive strength on all ports.
• Edge-selectable interrupt and LPM3.5, LPM4.5 wakeup input capability available for all bits of ports P1
and P2.
• Read-write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 Through P11) or word-wise in pairs (PA Through PF).
6.11.6 Port Mapping Controller (Link to User's Guide)
The port mapping controller allows flexible and reconfigurable mapping of digital functions to Ports P2, P3,
and P4.
VALUE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Table 6-11. Port Mapping Mnemonics and Functions
PxMAPy MNEMONIC
PM_NONE
PM_UCA0RXD
PM_UCA0SOMI
PM_UCA0TXD
PM_UCA0SIMO
PM_UCA0CLK
PM_UCA0STE
PM_UCA1RXD
PM_UCA1SOMI
PM_UCA1TXD
PM_UCA1SIMO
PM_UCA1CLK
PM_UCA1STE
PM_UCA2RXD
PM_UCA2SOMI
PM_UCA2TXD
PM_ UCA2SIMO
PM_UCA2CLK
PM_UCA2STE
PM_UCA3RXD
PM_UCA3SOMI
PM_UCA3TXD
PM_ UCA3SIMO
PM_UCA3CLK
PM_UCA3STE
PM_UCB0SIMO
PM_UCB0SDA
PM_UCB0SOMI
PM_UCB0SCL
PM_UCB0CLK
PM_UCB0STE
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
None
DVSS
eUSCI_A0 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A0 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A0 clock input/output (direction controlled by eUSCI)
eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A1 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A1 clock input/output (direction controlled by eUSCI)
eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_A2 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A2 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A2 clock input/output (direction controlled by eUSCI)
eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_A3 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A3 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A3 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A3 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A3 clock input/output (direction controlled by eUSCI)
eUSCI_A3 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)
eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)
eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
eUSCI_B0 clock input/output (direction controlled by eUSCI)
eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI)
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Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A