MSP430F6779A Datasheet, PDF (20/176 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
SLAS982 – MAY 2014
www.ti.com
TERMINAL
NAME
P2.3/PM_TA1.0/COM7
LCDCAP/R33
P2.4/PM_TA2.0/R23
P2.5/PM_UCB0SOMI/
PM_UCB0SCL/LCDREF/
R13
P2.6/PM_UCB0SIMO/
PM_UCB0SDA/R03
P2.7/PM_UCB0CLK/CB2
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
P3.1/PM_UCA0TXD/
PM_UCA0SIMO/S39
P3.2/PM_UCA0CLK/S38
P3.3/PM_UCA1CLK/S37
Table 4-4. Terminal Functions – PZ Package (continued)
NO. I/O⁽¹⁾
PZ
DESCRIPTION
General-purpose digital I/O with port interrupt and mappable secondary function
45 I/O _{Default Mapping: Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output}
LCD common output COM7 for LCD backplane
LCD capacitor connection
46 I/O _{Input/output port of most positive analog LCD voltage (V1)}
CAUTION: This pin must be connected to DVSS if not used.
General-purpose digital I/O with port interrupt and mappable secondary function
47 I/O _{Default Mapping: Timer TA2 CCR0 capture: CCI0A input, compare: Out0 output}
Input/output port of second most positive analog LCD voltage (V2)
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 SPI slave out, master in
48 I/O _{Default mapping: eUSCI_B0 I}2_{C clock}
External reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)
General-purpose digital I/O with port interrupt and mappable secondary function
49 I/O ^{Default mapping: eUSCI_B0 SPI slave in, master out}
Default mapping: eUSCI_B0 I²C data
Input/output port of lowest analog LCD voltage (V5)
General-purpose digital I/O with port interrupt and mappable secondary function
50 I/O _{Default mapping: eUSCI_B0 clock input/output}
Comparator_B input CB2
General-purpose digital I/O with mappable secondary function
51 I/O _{Default mapping: eUSCI_A0 UART receive data}
Default mapping: eUSCI_A0 SPI slave out, master in
General-purpose digital I/O with mappable secondary function
52 I/O ^{Default mapping: eUSCI_A0 UART transmit data}
Default mapping: eUSCI_A0 SPI slave in, master out
LCD segment output S39
General-purpose digital I/O with mappable secondary function
53 I/O _{Default mapping: eUSCI_A0 clock input/output}
LCD segment output S38
General-purpose digital I/O with mappable secondary function
54 I/O _{Default mapping: eUSCI_A1 clock input/output}
LCD segment output S37
20
Terminal Configuration and Functions
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A