LM3S5739 Datasheet, PDF (778/856 Pages) Texas Instruments – Stellaris® LM3S5739 Microcontroller

Signal Tables
Table 20-1. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PB0
I/O
TTL
GPIO port B bit 0.
66
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
PB1
I/O
TTL
GPIO port B bit 1.
67
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
68
VDD
-
Power Positive supply for I/O and some logic.
69
GND
-
Power Ground reference for logic and I/O pins.
70
USB0DM
I/O
Analog Bidirectional differential data pin (D- per USB specification) for
USB0.
71
USB0DP
I/O
Analog Bidirectional differential data pin (D+ per USB specification) for
USB0.
PB2
I/O
TTL
GPIO port B bit 2.
72
I2C0SCL
I/O
OD
I²C module 0 clock.
73
USB0RBIAS
O
Analog 9.1-kΩ resistor (1% precision) used internally for USB analog
circuitry.
PE0
I/O
TTL
GPIO port E bit 0.
74
SSI1Clk
I/O
TTL
SSI module 1 clock.
PE1
I/O
TTL
GPIO port E bit 1.
75
SSI1Fss
I/O
TTL
SSI module 1 frame.
PH4
I/O
TTL
GPIO port H bit 4.
76
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
PC3
I/O
TTL
GPIO port C bit 3.
77
SWO
O
TTL
JTAG TDO and SWO.
TDO
O
TTL
JTAG TDO and SWO.
PC2
I/O
TTL
GPIO port C bit 2.
78
TDI
I
TTL
JTAG TDI.
PC1
I/O
TTL
GPIO port C bit 1.
79
SWDIO
I/O
TTL
JTAG TMS and SWDIO.
TMS
I/O
TTL
JTAG TMS and SWDIO.
PC0
I/O
TTL
GPIO port C bit 0.
80
SWCLK
I
TTL
JTAG/SWD CLK.
TCK
I
TTL
JTAG/SWD CLK.
81
VDD
-
Power Positive supply for I/O and some logic.
82
GND
-
Power Ground reference for logic and I/O pins.
PH3
I/O
TTL
GPIO port H bit 3.
83
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
84
PH2
I/O
TTL
GPIO port H bit 2.
85
PH1
I/O
TTL
GPIO port H bit 1.
PH0
I/O
TTL
GPIO port H bit 0.
86
CCP6
I/O
TTL
Capture/Compare/PWM 6.
778
November 17, 2011
Texas Instruments-Production Data