LM3S5739 Datasheet, PDF (32/856 Pages) Texas Instruments – Stellaris® LM3S5739 Microcontroller

Revision History
Table 1. Revision History (continued)
Date
July 2009
Revision Description
5920 ■ Clarified Power-on reset and RST pin operation; added new diagrams.
■ Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL)
registers.
■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.
■ Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1
registers.
■ Special bulk handling and packet splitting has never been supported as the µDMA module can
support the same function. As a result, all references to these topics has been removed. Bit 7 in
the USBTXCSRLn register only functions as NAKTO in Host mode and is reserved in Device mode.
In addition, bit 0 in the USBRXCSRHn register is reserved.
■ The DISCON and CONN bits in the USBIS and USBIE registers are not available in Device mode.
When the USB controller is acting as a self-powered Device, a GPIO input or analog comparator
input must be connected to VBUS and configured to generate an interrupt when the VBUS level
drops. This interrupt is used to disable the pullup resistor on the USB0DP signal.
■ Changed buffer type for WAKE pin to TTL.
■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added
E_IR(Internal voltage reference error) parameter.
■ Changed ordering numbers.
■ Additional minor data sheet clarifications and corrections.
April 2009
5368
■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 167).
■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
of the output divisor.
■ Corrected bits 2:1 in I2CSIMR, I2CSRIS, I2CSMIS, and I2CSICR registers to be reserved bits
(cannot interrupt on start and stop conditions).
■ Corrected bits 15:11 in USBTXMAXP0/1/2 and USBRXMAXP0/1/2 registers to be reserved bits
(cannot define multiplier).
■ Additional minor data sheet clarifications and corrections.
January 2009
4724
■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.
■ Added clarification as to what happens when the SSI in slave mode is required to transmit but there
is no data in the TX FIFO.
■ Added section called "Setting the Device Address" for special considerations when writing the
USBFADDR register.
■ Corrected USBEPIDX to be an 8-bit register.
■ Added comparator operating mode tables.
■ Corrected pin types of signals RST to "in" and USB0RBIAS to "out".
■ Additional minor data sheet clarifications and corrections.
November 2008
4283
■ Revised High-Level Block Diagram.
■ Additional minor data sheet clarifications and corrections were made.
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November 17, 2011
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