LM3S5739 Datasheet, PDF (393/856 Pages) Texas Instruments – Stellaris® LM3S5739 Microcontroller

Stellaris® LM3S5739 Microcontroller
Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528
Important: This register is only valid for ports D and E.
If any pin is to be used as an ADC input, the appropriate bit in GPIOAMSEL must be
written to 1 to disable the analog isolation circuit.
The GPIOAMSEL register controls isolation circuits to the analog side of a unified I/O pad. Because
the GPIOs may be driven by a 5V source and affect analog operation, analog circuitry requires
isolation from the pins when not used in their analog function.
Each bit of this register controls the isolation circuitry for circuits that share the same pin as the
GPIO bit lane.
GPIO Analog Mode Select (GPIOAMSEL)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
Offset 0x528
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
GPIOAMSEL
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7:4
Name
reserved
GPIOAMSEL
Type
RO
R/W
Reset
0x00
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Analog Mode Select
Value Description
0 Analog function of the pin is disabled, the isolation is enabled,
and the pin is capable of digital functions as specified by the
other GPIO configuration registers.
1 Analog function of the pin is enabled, the isolation is disabled,
and the pin is capable of analog functions.
Note: This register and bits are required only for GPIO bit lanes that
share analog function through a unified I/O pad.
The reset state of this register is 0 for all bit lanes.
November 17, 2011
393
Texas Instruments-Production Data