LM3S5739 Datasheet, PDF (12/856 Pages) Texas Instruments – Stellaris® LM3S5739 Microcontroller

Table of Contents
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 548
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 549
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 549
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 550
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 551
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 551
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 552
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 553
Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 553
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 554
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 555
Figure 15-1. I²C Block Diagram ............................................................................................. 585
Figure 15-2. I²C Bus Configuration ........................................................................................ 586
Figure 15-3. START and STOP Conditions ............................................................................. 586
Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 587
Figure 15-5. R/S Bit in First Byte ............................................................................................ 587
Figure 15-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 587
Figure 15-7. Master Single SEND .......................................................................................... 591
Figure 15-8. Master Single RECEIVE ..................................................................................... 592
Figure 15-9. Master Burst SEND ........................................................................................... 593
Figure 15-10. Master Burst RECEIVE ...................................................................................... 594
Figure 15-11. Master Burst RECEIVE after Burst SEND ............................................................ 595
Figure 15-12. Master Burst SEND after Burst RECEIVE ............................................................ 596
Figure 15-13. Slave Command Sequence ................................................................................ 597
Figure 16-1. CAN Controller Block Diagram ............................................................................ 622
Figure 16-2. CAN Data/Remote Frame .................................................................................. 623
Figure 16-3. Message Objects in a FIFO Buffer ...................................................................... 631
Figure 16-4. CAN Bit Time .................................................................................................... 635
Figure 17-1. USB Module Block Diagram ............................................................................... 668
Figure 18-1. Analog Comparator Module Block Diagram ......................................................... 762
Figure 18-2. Structure of Comparator Unit .............................................................................. 763
Figure 18-3. Comparator Internal Reference Structure ............................................................ 764
Figure 19-1. 100-Pin LQFP Package Pin Diagram .................................................................. 774
Figure 22-1. Load Conditions ................................................................................................ 794
Figure 22-2. JTAG Test Clock Input Timing ............................................................................. 797
Figure 22-3. JTAG Test Access Port (TAP) Timing .................................................................. 797
Figure 22-4. External Reset Timing (RST) .............................................................................. 798
Figure 22-5. Power-On Reset Timing ..................................................................................... 798
Figure 22-6. Brown-Out Reset Timing .................................................................................... 798
Figure 22-7. Software Reset Timing ....................................................................................... 798
Figure 22-8. Watchdog Reset Timing ..................................................................................... 799
Figure 22-9. Hibernation Module Timing ................................................................................. 800
Figure 22-10. ADC Input Equivalency Diagram ......................................................................... 801
Figure 22-11. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 802
Figure 22-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 802
Figure 22-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 803
Figure 22-14. I²C Timing ......................................................................................................... 804
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November 17, 2011
Texas Instruments-Production Data