LM3S5739 Datasheet, PDF (23/856 Pages) Texas Instruments – Stellaris® LM3S5739 Microcontroller

Stellaris® LM3S5739 Microcontroller
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Register 26:
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 529
UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 531
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 532
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 533
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 534
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 535
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 536
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 537
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 538
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 539
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 540
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 541
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 542
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 543
Synchronous Serial Interface (SSI) ............................................................................................ 544
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 558
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 560
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 562
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 563
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 565
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 566
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 568
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 569
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 570
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 571
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 572
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 573
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 574
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 575
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 576
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 577
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 578
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 579
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 580
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 581
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 582
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 583
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 584
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 600
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 601
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 605
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 606
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 607
Register 6: I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 608
Register 7: I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 609
Register 8: I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 610
Register 9: I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 611
November 17, 2011
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