LM3S5739 Datasheet, PDF (739/856 Pages) Texas Instruments – Stellaris® LM3S5739 Microcontroller

Stellaris® LM3S5739 Microcontroller
Register 65: USB Receive Control and Status Endpoint 1 High (USBRXCSRH1),
offset 0x117
Register 66: USB Receive Control and Status Endpoint 2 High (USBRXCSRH2),
offset 0x127
Register 67: USB Receive Control and Status Endpoint 3 High (USBRXCSRH3),
offset 0x137
Host
USBRXCSRHn is an 8-bit register that provides additional control and status bits for transfers
through the currently selected receive endpoint.
Device
Host Mode
USB Receive Control and Status Endpoint 1 High (USBRXCSRH1)
Base 0x4005.0000
Offset 0x117
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
AUTOCL AUTORQ DMAEN PIDERR DMAMOD DTWE
DT
reserved
Type R/W
R/W
R/W
RO
R/W
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
Bit/Field
7
Name
AUTOCL
Type
R/W
Reset
0
Description
Auto Clear
Value Description
0 No effect.
1 Enables the RXRDY bit to be automatically cleared when a packet
of USBRXMAXPn bytes has been unloaded from the receive
FIFO. When packets of less than the maximum packet size are
unloaded, RXRDY must be cleared manually. Care must be taken
when using µDMA to unload the receive FIFO as data is read
from the receive FIFO in 4 byte chunks regardless of the value
of the MAXLOAD field in the USBRXMAXPn register, see “DMA
Operation” on page 678.
6
AUTORQ
R/W
0
Auto Request
Value Description
0 No effect.
1 Enables the REQPKT bit to be automatically set when the RXRDY
bit is cleared.
Note: This bit is automatically cleared when a short packet is
received.
November 17, 2011
739
Texas Instruments-Production Data