LM3S5739 Datasheet, PDF (359/856 Pages) Texas Instruments – Stellaris® LM3S5739 Microcontroller

Stellaris® LM3S5739 Microcontroller
Table 9-3. GPIO Signals (100LQFP) (continued)
Pin Name
Pin Number Pin Type Buffer Type^a Description
PF3
59
I/O
TTL
GPIO port F bit 3.
PF4
58
I/O
TTL
GPIO port F bit 4.
PF5
46
I/O
TTL
GPIO port F bit 5.
PF6
43
I/O
TTL
GPIO port F bit 6.
PF7
42
I/O
TTL
GPIO port F bit 7.
PG0
19
I/O
TTL
GPIO port G bit 0.
PG1
18
I/O
TTL
GPIO port G bit 1.
PG2
17
I/O
TTL
GPIO port G bit 2.
PG3
16
I/O
TTL
GPIO port G bit 3.
PG4
41
I/O
TTL
GPIO port G bit 4.
PG5
40
I/O
TTL
GPIO port G bit 5.
PG6
37
I/O
TTL
GPIO port G bit 6.
PG7
36
I/O
TTL
GPIO port G bit 7.
PH0
86
I/O
TTL
GPIO port H bit 0.
PH1
85
I/O
TTL
GPIO port H bit 1.
PH2
84
I/O
TTL
GPIO port H bit 2.
PH3
83
I/O
TTL
GPIO port H bit 3.
PH4
76
I/O
TTL
GPIO port H bit 4.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
9.2 Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the four JTAG/SWD pins (PC[3:0]). The
JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1
and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins
back to their default state.
Each GPIO port is a separate hardware instantiation of the same physical block(see Figure
9-1 on page 360 and Figure 9-2 on page 361). The LM3S5739 microcontroller contains eight ports
and thus eight of these physical GPIO blocks.
November 17, 2011
359
Texas Instruments-Production Data