LM3S5739 Datasheet, PDF (162/856 Pages) Texas Instruments – Stellaris® LM3S5739 Microcontroller

JTAG Interface
4.1 Block Diagram
Figure 4-1. JTAG Module Block Diagram
TCK
TMS
TAP Controller
TDI
Instruction Register (IR)
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TDO
Cortex-M3
Debug
Port
4.2 Signal Description
Table 4-1 on page 162 lists the external signals of the JTAG/SWD controller and describes the
function of each. The JTAG/SWD controller signals are alternate functions for some GPIO signals,
however note that the reset state of the pins is for the JTAG/SWD function. The JTAG/SWD controller
signals are under commit protection and require a special process to be configured as GPIOs, see
“Commit Control” on page 363. The column in the table below titled "Pin Assignment" lists the GPIO
pin placement for the JTAG/SWD controller signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 378) is set to choose the JTAG/SWD function. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 355.
Table 4-1. JTAG_SWD_SWO Signals (100LQFP)
Pin Name
Pin Number Pin Type Buffer Type^a Description
SWCLK
80
I
TTL
JTAG/SWD CLK.
SWDIO
79
I/O
TTL
JTAG TMS and SWDIO.
SWO
77
O
TTL
JTAG TDO and SWO.
TCK
80
I
TTL
JTAG/SWD CLK.
TDI
78
I
TTL
JTAG TDI.
TDO
77
O
TTL
JTAG TDO and SWO.
TMS
79
I/O
TTL
JTAG TMS and SWDIO.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
162
November 17, 2011
Texas Instruments-Production Data