LM3S5739 Datasheet, PDF (50/856 Pages) Texas Instruments – Stellaris® LM3S5739 Microcontroller

Architectural Overview
1.4.3.2
1.4.4
1.4.4.1
programming with fully configurable input source, trigger events, interrupt generation, and sequence
priority.
Analog Comparators (see page 761)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S5739 microcontroller provides two independent integrated analog comparators that can
be configured to drive an output or generate an interrupt or ADC event.
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
Serial Communications Peripherals
The LM3S5739 controller supports both asynchronous and synchronous serial communications
with:
■ Three fully programmable 16C550-type UARTs
■ Two SSI modules
■ Two I²C modules
■ One USB 2.0 full-speed controller
■ One CAN unit
UART (see page 500)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S5739 controller includes three fully programmable 16C550-type UARTs that support data
transfer speeds up to 3.125 Mbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and receive (RX) FIFOs reduce CPU interrupt service loading. The
UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
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November 17, 2011
Texas Instruments-Production Data