LM3S5739 Datasheet, PDF (680/856 Pages) Texas Instruments – Stellaris® LM3S5739 Microcontroller

Universal Serial Bus (USB) Controller
mode, the maximum packet size for the given endpoint must be set prior to sending or receiving
data.
Configuring each endpoint’s FIFO involves reserving a portion of the overall USB FIFO RAM to
each endpoint. The total FIFO RAM available is 4 Kbytes with the first 64 bytes reserved for endpoint
0. The endpoint’s FIFO must be at least as large as the maximum packet size. The FIFO can also
be configured as a double-buffered FIFO so that interrupts occur at the end of each packet and
allow filling the other half of the FIFO.
If operating as a Device, the USB Device controller's soft connect must be enabled when the Device
is ready to start communications, indicating to the Host controller that the Device is ready to start
the enumeration process. If operating as a Host controller, the Device soft connect must be disabled
and power must be provided to VBUS via the USB0EPEN signal.
17.5
Register Map
Table 17-5 on page 680 lists the registers. All addresses given are relative to the USB base address
of 0x4005.0000. Note that the USB controller clock must be enabled before the registers can be
programmed (see page 233). There must be a delay of 3 system clocks after the USB module clock
is enabled before any USB module registers are accessed.
Table 17-5. Universal Serial Bus (USB) Controller Register Map
Offset Name
Type
Reset
Description
0x000 USBFADDR
0x001 USBPOWER
0x002 USBTXIS
0x004 USBRXIS
0x006 USBTXIE
0x008 USBRXIE
0x00A USBIS
0x00B USBIE
0x00C USBFRAME
0x00E USBEPIDX
0x00F USBTEST
0x020 USBFIFO0
0x024 USBFIFO1
0x028 USBFIFO2
0x02C USBFIFO3
0x060 USBDEVCTL
0x062 USBTXFIFOSZ
0x063 USBRXFIFOSZ
0x064 USBTXFIFOADD
R/W
0x00
USB Device Functional Address
R/W
0x20
USB Power
RO
0x0000
USB Transmit Interrupt Status
RO
0x0000
USB Receive Interrupt Status
R/W
0x000F
USB Transmit Interrupt Enable
R/W
0x000E
USB Receive Interrupt Enable
RO
0x00
USB General Interrupt Status
R/W
0x06
USB Interrupt Enable
RO
0x0000
USB Frame Value
R/W
0x00
USB Endpoint Index
R/W
0x00
USB Test Mode
R/W
0x0000.0000 USB FIFO Endpoint 0
R/W
0x0000.0000 USB FIFO Endpoint 1
R/W
0x0000.0000 USB FIFO Endpoint 2
R/W
0x0000.0000 USB FIFO Endpoint 3
RO
0x80
USB Device Control
R/W
0x00
USB Transmit Dynamic FIFO Sizing
R/W
0x00
USB Receive Dynamic FIFO Sizing
R/W
0x0000
USB Transmit FIFO Start Address
See
page
684
685
688
689
690
691
692
695
698
699
700
702
702
702
702
703
704
704
705
680
November 17, 2011
Texas Instruments-Production Data