LM3S5739 Datasheet, PDF (5/856 Pages) Texas Instruments – Stellaris® LM3S5739 Microcontroller

Stellaris® LM3S5739 Microcontroller
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6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
6.6
Hibernation Module .............................................................................................. 243
Block Diagram ............................................................................................................ 244
Signal Description ....................................................................................................... 244
Functional Description ................................................................................................. 245
Register Access Timing ............................................................................................... 245
Clock Source .............................................................................................................. 245
Battery Management ................................................................................................... 247
Real-Time Clock .......................................................................................................... 247
Battery-Backed Memory .............................................................................................. 247
Power Control ............................................................................................................. 248
Initiating Hibernate ...................................................................................................... 248
Interrupts and Status ................................................................................................... 248
Initialization and Configuration ..................................................................................... 249
Initialization ................................................................................................................. 249
RTC Match Functionality (No Hibernation) .................................................................... 249
RTC Match/Wake-Up from Hibernation ......................................................................... 249
External Wake-Up from Hibernation .............................................................................. 250
RTC/External Wake-Up from Hibernation ...................................................................... 250
Register Map .............................................................................................................. 250
Register Descriptions .................................................................................................. 251
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.3.1
7.3.2
7.4
7.5
7.6
7.7
Internal Memory ................................................................................................... 265
Block Diagram ............................................................................................................ 265
Functional Description ................................................................................................. 265
SRAM Memory ............................................................................................................ 265
ROM Memory ............................................................................................................. 266
Flash Memory ............................................................................................................. 266
Flash Memory Initialization and Configuration ............................................................... 268
Flash Programming ..................................................................................................... 268
Nonvolatile Register Programming ............................................................................... 268
Register Map .............................................................................................................. 269
ROM Register Descriptions (System Control Offset) ...................................................... 270
Flash Register Descriptions (Flash Control Offset) ......................................................... 271
Flash Register Descriptions (System Control Offset) ...................................................... 279
8
Micro Direct Memory Access (μDMA) ................................................................ 294
8.1 Block Diagram ............................................................................................................ 295
8.2 Functional Description ................................................................................................. 295
8.2.1 Channel Assigments .................................................................................................... 296
8.2.2 Priority ........................................................................................................................ 296
8.2.3 Arbitration Size ............................................................................................................ 296
8.2.4 Request Types ............................................................................................................ 297
8.2.5 Channel Configuration ................................................................................................. 297
8.2.6 Transfer Modes ........................................................................................................... 299
8.2.7 Transfer Size and Increment ........................................................................................ 307
8.2.8 Peripheral Interface ..................................................................................................... 307
8.2.9 Software Request ........................................................................................................ 307
8.2.10 Interrupts and Errors .................................................................................................... 308
8.3 Initialization and Configuration ..................................................................................... 308
8.3.1 Module Initialization ..................................................................................................... 308
November 17, 2011
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