LM3S5739 Datasheet, PDF (679/856 Pages) Texas Instruments – Stellaris® LM3S5739 Microcontroller

Stellaris® LM3S5739 Microcontroller
17.4
17.4.1
17.4.2
See “Micro Direct Memory Access (μDMA)” on page 294 for more details about programming the
μDMA controller.
Initialization and Configuration
To use the USB Controller, the peripheral clock must be enabled via the RCGC2 register (see
page 233). In addition, the clock to the appropriate GPIO module must be enabled via the RCGC2
register in the System Control module (see page 233). To find out which GPIO port to enable, refer
to Table 20-3 on page 784.
The initial configuration in all cases requires that the processor enable the USB controller and USB
controller’s physical layer interface (PHY) before setting any registers. The next step is to enable
the USB PLL so that the correct clocking is provided to the PHY. To ensure that voltage is not
supplied to the bus incorrectly, the external power control signal, USB0EPEN, should be negated on
start up by configuring the USB0EPEN and USB0PFLT pins to be controlled by the USB controller
and not exhibit their default GPIO behavior.
The USB controller provides a method to set the current operating mode of the USB controller. This
register should be written with the desired default mode so that the controller can respond to external
USB events.
Pin Configuration
When using the Device controller portion of the USB controller in a system that also provides Host
functionality, the power to VBUS must be disabled to allow the external Host controller to supply
power. Usually, the USB0EPEN signal is used to control the external regulator and should be negated
to avoid having two devices driving the USB0VBUS power pin on the USB connector.
When the USB controller is acting as a Host, it is in control of two signals that are attached to an
external voltage supply that provides power to VBUS. The Host controller uses the USB0EPEN signal
to enable or disable power to the USB0VBUS pin on the USB connector. An input pin, USB0PFLT,
provides feedback when there has been a power fault on VBUS. The USB0PFLT signal can be
configured to either automatically negate the USB0EPEN signal to disable power, and/or it can
generate an interrupt to the interrupt controller to allow software to handle the power fault condition.
The polarity and actions related to both USB0EPEN and USB0PFLT are fully configurable in the USB
controller. The controller also provides interrupts on Device insertion and removal to allow the Host
controller code to respond to these external events.
Endpoint Configuration
To start communication in Host or Device mode, the endpoint registers must first be configured. In
Host mode, this configuration establishes a connection between an endpoint register and an endpoint
on a Device. In Device mode, an endpoint must be configured before enumerating to the Host
controller.
In both cases, the endpoint 0 configuration is limited because it is a fixed-function, fixed-FIFO-size
endpoint. In Device and Host modes, the endpoint requires little setup but does require a
software-based state machine to progress through the setup, data, and status phases of a standard
control transaction. In Device mode, the configuration of the remaining endpoints is done once
before enumerating and then only changed if an alternate configuration is selected by the Host
controller. In Host mode, the endpoints must be configured to operate as control, bulk, interrupt or
isochronous mode. Once the type of endpoint is configured, a FIFO area must be assigned to each
endpoint. In the case of bulk, control and interrupt endpoints, each has a maximum of 64 bytes per
transaction. Isochronous endpoints can have packets with up to 1023 bytes per packet. In either
November 17, 2011
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