DS90UH928Q-Q1 Datasheet, PDF (61/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

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DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
11.1.1 CML Interconnect Guidelines
See Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines SNLA008 and
Application Note 905 Transmission Line RAPIDESIGNER Operation and Applications Guide SNLA035 for
full details.
• Use 100 Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– – S = space between the pair
– – 2S = space between pairs
– – 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500 Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual (SNLA187).
11.2 Layout Example
High-Speed Traces
AC Capacitors
Length-Matched
OpenLDI Traces
Figure 44. DS90UH928Q-Q1 Deserializer Example Layout
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