DS90UH928Q-Q1 Datasheet, PDF (18/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
8 Detailed Description
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8.1 Overview
The DS90UH928Q-Q1 receives a 35-bit symbol over a single serial FPD-Link III pair operating at up to 2.975
Gbps line rate and converts this stream into an FPD-Link Interface (4 LVDS data channels + 1 LVDS Clock). The
FPD-Link III serial stream contains an embedded clock, video control signals, and the DC-balanced video data
and audio data which enhance signal quality to support AC coupling.
The DS90UH928Q-Q1 deserializer attains lock to a data stream without the use of a separate reference clock
source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the
serializer regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the
incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers
the clock and data by extracting the embedded clock information, validating then deserializing the incoming data
stream. It also applies decryption through a High-Bandwidth Digital Content Protection (HDCP) Cipher to this
video and audio data stream following reception of the data from the FPD-Link III decoder. On-chip non-volatile
memory stores the HDCP keys. All key exchange is done through the FPD-Link III bidirectional control interface.
The decrypted FPD-Link LVDS video bus is provided to the display.
The DS90UH928Q-Q1 deserializer incorporates an I²C-compatible interface. The I²C-compatible interface allows
programming of serializer or deserializer devices from a local host controller. In addition, the
serializer/deserializer devices incorporate a bidirectional control channel (BCC) that allows communication
between serializer/deserializer as well as remote I2C slave devices.
The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward
channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to
serializer). Through this interface, the BCC provides a mechanism to bridge I²C transactions across the serial link
from one I²C bus to another. The implementation allows for arbitration with other I²C compatible masters at either
side of the serial link.
The DS90UH928Q-Q1 deserializer is intended for use with DS90UH925Q-Q1 or DS90UH927Q-Q1 serializers,
but is also backward compatible with DS90UR905Q and DS90UR907Q FPD-Link II serializers.
8.2 Functional Block Diagram
CMF
RIN+
RIN-
BISTEN
BISTC
LFMODE
MAPSEL
PDB
SCL
SCA
IDx
MODE_SEL
REGULATOR
Timing and
Control
Error
Detector
Clock and
Data
Recovery
OEN
OSS_SEL
TxOUT3±
TxOUT2±
TxOUT1±
TxOUT0±
TxCLKOUT±
8
I2S / GPIO
PASS
LOCK
18
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