DS90UH928Q-Q1 Datasheet, PDF (1/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

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DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
DS90UH928Q-Q1 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With
HDCP
1 Features
•1 Qualified for Automotive Applications AEC-Q100
– Device Temperature Grade 2: -40°C to +105°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level ±8 kV
– Device CDM ESD Classification Level C6
• Integrated HDCP Cipher Engine with On-Chip Key
Storage
• Supports HDCP Repeater Application
• Bidirectional Control Channel Interface with I²C
Compatible Serial Control Bus
• Low EMI FPD-Link Video Output
• Supports High Definition (720p) Digital Video
• RGB888 + VS, HS, DE and I2S Audio Supported
• 5 MHz to 85 MHz Pixel Clock Support
• Up to 4 I2S Digital Audio Outputs for Surround
Sound Applications
• 4 Bidirectional GPIO Channels with 2 Dedicated
Pins
• Single 3.3 V supply with 1.8 V or 3.3 V
Compatible LVCMOS I/O Interface
• AC-Coupled STP Interconnect Up to 10 Meters
• DC-Balanced and Scrambled Data with
Embedded Clock
• Adaptive Cable Equalization
• Image Enhancement (White Balance & Dithering)
and Internal Pattern Generation
• Backward Compatible Modes
2 Applications
• Automotive Displays for Navigation
• Rear Seat Entertainment Systems
3 Description
The DS90UH928Q-Q1 deserializer, in conjunction
with a DS90UH925Q-Q1 or DS90UH927Q-Q1
serializer, provides a solution for secure distribution of
content-protected digital video and audio within
automotive infotainment systems. The device
converts a high-speed serialized interface with an
embedded clock, delivered over a single signal pair
(FPD-Link III), to four LVDS data/control streams, one
LVDS clock pair (OpenLDI (FPD-Link)), and I2S
audio data. The digital video and audio data is
protected using the industry standard HDCP copy
protection scheme.The serial bus scheme, FPD-Link
III, supports high-speed forward channel data
transmission and low-speed full duplex back channel
communication over a single differential link.
Consolidation of audio, video data and control over a
single differential pair reduces the interconnect size
and weight, while also eliminating skew issues and
simplifying system design.
Adaptive input equalization of the serial input stream
provides compensation for transmission medium
losses and deterministic jitter. EMI is minimized by
the use of low voltage differential signaling.
The HDCP cipher engine is implemented in both the
serializer and deserializer. HDCP keys are stored in
on-chip memory.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UH928Q-Q1 WQFN (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Application Diagram
FPD-Link
VDDIO VDD33
(1.8V or 3.3V) (3.3V)
FPD-Link
(OpenLDI)
VDD33 VDDIO
(3.3V) (1.8V or 3.3V)
HOST
Graphics
Processor
RxIN3+/-
RxIN2+/-
RxIN1+/-
RxIN0+/-
RxCLKIN+/-
PDB
I2S AUDIO 6
(Surround)
SCL
SDA
IDx
DOUT+
DOUT-
DS90UH927Q
Serializer
FPD-Link III
1 Pair/AC Coupled
100Q STP Cable
CMF
CMF
OEN
OSS_SEL
PDB
MAPSEL
LFMODE
REPEAT
MAPSEL
LFMODE
REPEAT
BACKWD
BISTEN
MODE_SEL
RIN+
RIN-
DS90UH928Q
Deserializer
TxOUT3+/-
TxOUT2+/-
TxOUT1+/-
TxOUT0+/-
TxCLKOUT+/-
LOCK
PASS
6
I2S AUDIO
(Surround)
MCLK
SCL
SDA
IDx
LVDS Display
720p or Graphic
Processor
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.