DS90UH928Q-Q1 Datasheet, PDF (19/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

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DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
8.3 Feature Description
8.3.1 High Speed Forward Channel Data Transfer
The High-Speed Forward Channel is composed of a 35-bit frame containing video data, sync signals, HDCP, I²C,
and I2S audio transmitted from serializer to deserializer. Figure 19 illustrates the serial stream PCLK cycle. This
data payload is optimized for signal transmission over an AC-coupled link. Data is randomized, DC-balanced and
scrambled.
C1
C0
Figure 19. FPD-Link III Serial Stream
The device supports pixel clock ranges of 5 MHz to 15 MHz (LFMODE=1) and 15 MHz to 85 MHz (LFMODE=0).
This corresponds to an application payload rate range of 175 Mbps to 2.975 Gbps, with an actual line rate range
of 525 Mbps to 2.975 Gbps.
8.3.2 Low-Speed Back Channel Data Transfer
The Low-Speed Back Channel of the DS90UH928Q-Q1 provides bidirectional communication between the
display and host processor. The back channel control data is transferred over the single serial link along with the
high-speed forward data, DC balance coding and embedded clock information. Together, the forward channel
and back channel for the bidirectional control channel (BCC). This architecture provides a backward path across
the serial link together with a high speed forward channel. The back channel contains the I²C, HDCP, CRC and 4
bits of standard GPIO information with 10 Mbps line rate.
8.3.3 Backward Compatible Mode
The DS90UH928Q-Q1 is also backward compatible to the DS90UR905Q and DS90UR907Q FPD-Link II
serializes with 15 MHz to 65 MHz PCLK frequencies supported. It receives 28-bits of data over a single serial
FPD-Link II pair operating at a payload rate of 420 Mbps to 1.82 Gbps. This backward compatibility configuration
is provided through the MODE_SEL pin or programmed through the device control registers (Table 8). The
bidirectional control channel, HDCP, bidirectional GPIOs, I2S, and interrupt (INTB) are not active in this mode.
However, local I²C access to the serializer is still available.
8.3.4 Input Equalization
An FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces
medium-induced deterministic jitter. It supports STP cables up to 10 meters total cable length with 3 inline
connectors at maximum serializer stream payload rate of 2.975 Gbps.
The adaptive equalizer may be set to a Long Cable Mode (LCBL), using the MODE_SEL pin (Table 6). This
mode is typically used with longer cables where it may be desirable to start adaptive equalization from a higher
default gain. In this mode, the device attempts to lock from a minimum floor AEQ value, defined by a value
stored in the control registers (Table 8).
8.3.5 Common Mode Filter Pin (CMF)
The deserializer provides access to the center tap of the internal CML termination. A 0.1 μF capacitor must be
connected from this pin to GND for additional common-mode filtering of the differential pair (Figure 39). This
increases noise rejection capability in high-noise environments.
8.3.6 Power Down (PDB)
The deserializer has a PDB input pin to enable or power down the device. This pin may be controlled by an
external device, or through V_DDIO, where V_DDIO = 3 V to 3.6 V or V_DD33. To save power, disable the link when the
display is not needed (PDB = LOW). Ensure that this pin is not driven HIGH before V_DD33 and V_DDIO have
reached final levels. When PDB is driven low, ensure that the pin is driven to 0 V for at least 1.5 ms before
releasing or driving high (See ). If the PDB is pulled up to V_DDIO = 3 V to 3.6 V or V_DD33 directly, a 10 kΩ pullup
resistor and a >10 µF capacitor to ground are required (see Figure 39 ).
Toggling PDB low will POWER DOWN the device and RESET all control registers to default. During this time,
PDB must be held low for a minimum of 2 ms (see ).
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