DS90UH928Q-Q1 Datasheet, PDF (59/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

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Power Up Requirements and PDB Pin (continued)
t₀
VDDIO
GND
t₃
VDD33
GND
t₁
PDB^(*)
GND
V_{PDB_HIGH}
V_{PDB_LOW}
DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
VDD33
t₄
(*) _{It is recommended to assert PDB (active High) with a microcontroller rather than an RC filter}
network to help ensure proper sequencing of PDB pin after settling of power supplies.
Figure 43. Power Sequence
Table 10. Power-Up Sequencing Constraints
Symbol
Description
Test Conditions
Min
Typ
Max
Units
VDDIO
VDDIO voltage range
3.0
3.6
V
1.71
1.89
V
VDD33
VDD33 voltage range
3.0
3.6
V
PDB LOW threshold
V_{PDB_LOW}
Note: V_PDB must not exceed
limit for respective I/O voltage
VDDIO = 3.3V ± 10%
0.8
V
before 90% voltage of VDD33
V_{PDB_HIGH}
t₀
PDB HIGH threshold
VDDIO rise time
VDDIO = 3.3V ± 10%
These time constants are specified for
rise time of power supply voltage ramp 0.05
(10% - 90%)
2.0
V
1.5
ms
These time constants are specified for
t₃
VDD33 rise time
rise time of power supply voltage ramp 0.05
(10% - 90%)
1.5
ms
V_IL of rising edge (VDDIO ) to V_IL of
rising edge (VDD33)
t₁
VDD33 delay time
The power supplies may be ramped
0
ms
simultaneously. If sequenced, VDDIO
must be first.
The part is powered up after the startup
time has elapsed from the moment PDB
t₄
Startup time
goes HIGH. Local I2C is available to
read/write DS90Ux928Q-Q1 registers
after this time.
1
ms
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