DS90UH928Q-Q1 Datasheet, PDF (47/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

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DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
Register Maps (continued)
Table 8. Serial Control Bus Registers^{(1) (2)} (continued)
ADD
(dec)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
36
0x24 BIST Control
7:4
0x08
Reserved
3
RW
BIST Pin
Config
BIST Pin Configuration
0: BIST enabled from register
1: BIST enabled from pin (default)
2:1
RW
OSC Clock
Source
Internal OSC clock select for Functional Mode or
BIST. Functional Mode when PCLK is not present and
0x03[1]=1.
00: 33 MHz Oscillator (default)
01: 33 MHz Oscillator
Note: In LFMODE=1, the internal oscillator is 12.5
MHz
0
RW
BIST
Enable
BIST Control
0: Disabled (default)
1: Enabled
37
0x25 BIST Error
7:0
R
0x00
BIST Error
Count
Errors Detected During BIST
Records the number (up to 255) of forward-channel
errors detected during BIST. The value stored in this
register is only valid after BIST terminates (BISTEN =
0). Resets on PDB = 0 or start of another BIST
(BISTEN = 1).
38
0x26 SCL High Time 7:0
RW
0x83
SCL High
Time
I2C Master SCL High Time
This field configures the high pulse width of the SCL
output when the deserializer is the Master on the local
I2C bus. Units are 50 ns for the nominal oscillator
clock frequency.
39
0x27 SCL Low Time 7:0
RW
0x84
SCL Low
Time
I2C SCL Low Time
This field configures the low pulse width of the SCL
output when the deserializer is the Master on the local
I2C bus. This value is also used as the SDA setup
time by the I2C Slave for providing data prior to
releasing SCL during accesses over the Bidirectional
Control Channel. Units are 50 ns for the nominal
oscillator clock frequency.
40
0x28 Data Path
Control 2
7
RW
0x00 Block I2S Override Forward Channel Configuration
Auto Config 0: Enable forward-channel loading of this register
1: Disable loading of this register from the forward
channel, keeping local values intact
6:4
Reserved
3
RW
Aux I2S
Enable
Auxiliary I2S Channel Enable
0: Normal GPIO[1:0] operation
1: Enable Aux I2S channel on GPIO1 (AUX word
select) and GPIO0 (AUX data)
2
RW
I2S Disable Disable All I2S Outputs
0: I2S Outputs Enabled (default)
1: I2S Outputs Disabled
1
Reserved
0
RW
I2S
Surround
Enable 5.1- or 7.1-channel I2S audio transport
0: 2-channel or 4-channel I2S audio is enabled as
configured in register or MODE_SEL (default)
1: 5.1- or 7.1-channel audio is enabled
Note that I2S Data Island Transport is the only option
for surround audio. Also note that in a repeater, this
bit may be overridden by the in-band I2S mode
detection.
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