DS90UH928Q-Q1 Datasheet, PDF (36/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
www.ti.com
To support HDCP Repeater operation, the RX includes the ability to control the downstream authentication
process, assemble the KSV list for downstream HDCP Receivers, and pass the KSV list to the upstream HDCP
Transmitter. An I²C master within the RX communicates with the I²C slave within the TX. The TX handles
authenticating with a downstream HDCP Receiver and makes status available through the I²C interface. The RX
monitors the transmit port status for each TX and reads downstream KSV and KSV list values from the TX.
In addition to the I²C interface used to control the authentication process, the HDCP Repeater implementation
includes two other interfaces. The FPD-Link LVDS interface outputs the unencrypted video data. In addition to
providing the video data, the LVDS interface communicates control information and packetized audio data. All
audio and video data is decrypted at the output of the HDCP Receiver and is re-encrypted by the HDCP
Transmitter. Figure 34 provides more detailed block diagram of a 1:2 HDCP repeater configuration.
If the repeater node includes a local output to a display, White Balancing and Hi-FRC dithering functions should
not be used as they will block encrypted I2S audio and HDCP authentication.
upstream
Transmitter
I2C
I2C
Master
HDCP Receiver
(RX)
FPD-Link
I2S Audio
HDCP Transmitter
TX
I2C
Slave
HDCP Transmitter
TX
I2C
Slave
FPD-Link III interfaces
Figure 34. HDCP 1:2 Repeater Configuration
downstream
Receiver
or
Repeater
downstream
Receiver
or
Repeater
8.5 Programming
8.5.1 Serial Control Bus
The DS90UH928Q-Q1 may also be configured by the use of an I²C compatible serial control bus. Multiple
devices may share the serial control bus (up to 10 device addresses supported). The device address is set via a
resistor divider (R1 and R2 — see Figure 35) connected to the IDx pin.
VDD33
HOST
SCL
SDA
VDD33
R1
VR2
IDx
4.7kQ
4.7kQ
R2
DES
SCL
SDA
To other
Devices
Copyright © 2016, Texas Instruments Incorporated
Figure 35. Serial Control Bus Connection
The serial control bus consists of two signals and an address configuration pin. SCL is a Serial Bus Clock
Input/Output. SDA is the Serial Bus Data Input/Output signal. Both SCL and SDA signals require an external
pullup resistor to V_DD33 or V_DDIO = 3 V to 3.6 V. For most applications, a 4.7 kΩ pullup resistor to V_DD33 is
recommended. The signals are either pulled HIGH, or driven LOW.
36
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