DS90UH928Q-Q1 Datasheet, PDF (49/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

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DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
Register Maps (continued)
Table 8. Serial Control Bus Registers^{(1) (2)} (continued)
ADD
(dec)
53
57
58
59
65
68
69
ADD
(hex)
Register Name
Bit
0x35 AEQ Control
7
6
5
4
3:0
0x39 PG Internal
7:2
Clock Enable
1
0
0x3A I2S DIVSEL
7
6:4
3:0
0x3B Adaptive EQ
7:6
Status
5:0
0x41 Link Error Count 7:5
4
3:0
0x44 Adaptive
7:5
Equalizer
Bypass
4
3:1
0
0x45 Adaptive EQ
7:4
MIN/MAX
3:0
Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
(hex)
0x00
0x00
0x00
0x03
0x60
0x88
Function Description
Reserved
AEQ
Restart
Restart AEQ adaptation from initial (Floor) values
0: Normal operation (default)
1: Restart AEQ adaptation
Note: This bit is not self-clearing. It must be set, then
reset.
LCBL
Override
Override LCBL Mode Set by MODE_SEL
0: LCBL controlled by MODE_SEL pin
1: LCBL controlled by register
LCBL
Set LCBL Mode
0: LCBL Mode disabled
1: LCBL Mode enabled. AEQ Floor value is controlled
from Adaptive EQ MIN/MAX register
Reserved
Reserved
PG INT
CLK
Enable Pattern Generator Internal Clock
This bit must be set to use the Pattern Generator
Internal Clock Generation
0: Pattern Generator with external PCLK
1: Pattern Generator with internal PCLK
See TI Application Note ( ) for details
Reserved
MCLK Div
Override
Override MCLK Divider Setting
0: No override for MCLK divider (default)
1: Override divider select for MCLK
MCLK Div See Table 4
Reserved
Reserved
EQ Status
Equalizer Status
Current equalizer level set by AEQ or Override
Register
Reserved
Link Error
Count
Enable
Enable serial link data integrity error count
1: Enable error count
0: Disable
Link Error
Count
Threshold
Link error count threshold. Counter is pixel clock
based. CLK0, CLK1, and DCA are monitored for link
errors, if error count is enabled Deserializer loose lock
once error count reaches threshold if disabled
Deserializer loose lock with one error.
EQ Stage 1 EQ Stage 1 select value. Used if adaptive EQ is
Select
bypassed. Used if adaptive EQ is bypassed.
Value
Reserved
EQ Stage 2 EQ Stage 2 select value. Used if adaptive EQ is
Select
bypassed Used if adaptive EQ is bypassed.
Value
Adaptive
EQ Bypass
Bypass Adaptive EQ
Overrides Adaptive EQ search and sets the EQ to the
static value configured in this register
0: Enable adaptive EQ (default)
1: Disable adaptive EQ (to write EQ select values)
Reserved
Adaptive
EQ Floor
Adaptive Equalizer Floor Value
Sets the AEQ floor value when Long Cable Mode
(LCBL) is enabled by register or MODE_SEL
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